Memory Module Buffer Chip Point-to-Point Bus Architecture
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Solution Overview
Problem
In existing memory systems, increasing memory density through multiple memory modules leads to speed limitations and performance degradation due to the multi-drop bus structure, where I/O buses are commonly connected to memory chips in a vertical direction, causing capacitance increases and signal transmission inefficiencies.
Innovation Solution
A memory system design where each memory module includes a buffer chip and multiple memory chips, with all buffer chips directly coupled to a controller through independent I/O buses, allowing data input and output to be performed in a single channel manner, and memory chips are divided into ranks in column units for efficient data selection and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory modules are connected through a common multi-drop bus structure, then memory density is increased, but operation speed and performance are degraded due to capacitance increase and signal transmission inefficiencies
Solution Approach 1:
The patent divides the memory system into multiple independent point-to-point channels, where each channel connects the controller directly to a specific memory module through dedicated I/O buses. This segmentation eliminates the shared multi-drop bus structure, reducing signal interference and capacitance effects while maintaining high memory density through multiple parallel channels.
2Quantity of substance
If multiple memory modules are connected through a common multi-drop bus structure, then memory density is increased, but operation performance is degraded due to capacitance increase
Solution Approach 1:
The patent implements independent point-to-point I/O bus channels for each memory module, segmenting the electrical connection paths. This reduces the total capacitance affecting each signal line and improves signal integrity, thereby enhancing operation performance and reliability while supporting high memory density through multiple channels.
Solution Approach 2:
The patent introduces buffer chips as intermediary components between the controller and memory chips. These buffer chips are directly coupled to the controller through dedicated I/O buses, acting as intermediaries that reduce signal degradation and capacitance effects, thereby improving operation performance while enabling high memory density configurations.
3Device complexity
If I/O buses are commonly coupled to memory chips in vertical direction, then device integration is achieved, but signal transmission efficiency is reduced due to physical distance effects
Solution Approach 1:
The patent transitions from a vertical stacking arrangement to a horizontal point-to-point connection architecture. By changing the spatial dimension of connections and introducing dedicated I/O bus channels that extend horizontally from the controller to each memory module, the system reduces the impact of vertical stacking limitations while maintaining high integration through multiple parallel channels.
Data Source
AI summary
A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.