Memory Module Burn-In Testing via Parallel Assembly
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Solution Overview
Problem
Current burn-in testing processes for memory modules are inefficient and costly, requiring multiple insertions and removals of individual DRAM chips, which is time-consuming and expensive, and often uses expensive automated-test-equipment (ATE) machines.
Innovation Solution
The process is improved by performing burn-in testing on assembled memory modules instead of individual DRAM chips, using a simpler memory module tester based on a personal computer motherboard, which reduces the number of insertion and removal steps and lowers testing costs by allowing parallel testing of multiple DRAM chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If burn-in testing is performed on individual DRAM chips before module assembly, then reliability of individual chips is improved, but manufacturing cost and time increase due to multiple insertions and removals
Solution Approach 1:
The patent performs preliminary burn-in testing on individual DRAM chips before module assembly to eliminate infant mortality failures early. This preliminary action ensures chip reliability while allowing full functional testing to be deferred until after module assembly, thereby improving manufacturing efficiency by avoiding repeated handling of individual chips.
Solution Approach 2:
The testing process is segmented into two distinct phases: (1) burn-in testing of individual DRAM chips before assembly, and (2) full functional testing of the complete memory module after assembly. This segmentation allows each testing phase to be optimized independently, resolving the contradiction between reliability and manufacturing efficiency.
2Reliability
If full functional testing is performed on individual DRAM chips before assembly, then chip functionality is verified, but testing cost and time increase
Solution Approach 1:
The patent performs preliminary burn-in testing to stress and stabilize individual DRAM chips before assembly, which accelerates failure manifestation. Full functional testing is then performed once on the complete module, reducing total testing time compared to performing exhaustive functional tests on each individual chip separately.
Solution Approach 2:
The patent merges multiple individual chip testing operations into a single module-level functional test. By combining the testing of multiple DRAM chips into one unified module test, the patent reduces total testing time and resource consumption while maintaining comprehensive functionality verification.
3Reliability
If multiple insertions and removals of individual DRAM chips are performed, then comprehensive testing is achieved, but operator time and handling costs increase
Solution Approach 1:
The patent performs preliminary burn-in testing on individual DRAM chips to screen out defective units before they are assembled into modules. This preliminary action ensures testing completeness by catching failures early, while reducing operator workload by eliminating the need for repeated insertions and removals during subsequent functional testing.
Solution Approach 2:
The testing process is segmented into automated burn-in testing of individual chips followed by module assembly, and then single-time functional testing of the complete module. This segmentation reduces manual handling operations while maintaining comprehensive testing coverage through the combination of burn-in and functional test results.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces operator time and handling costs, lowers equipment costs, and allows for more efficient testing of memory modules, enhancing reliability while keeping manufacturing costs down.
Implementation Method 1
DRAM chips can be heated and have higher power-supply voltages (Vcc) applied to stress the DRAM chips and speed up the occurrence of failures
Implementation Method 2
DRAM chips can be heated and have higher power-supply voltages (Vcc) applied to stress the DRAM chips and speed up the occurrence of failures
Data Source
AI summary
Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory modules are stressed during burn-in by high temperatures and applied voltages. After burn-in, the memory modules are removed from the memory-module burn-in boards and extensively tested. Functional tests include many test patterns to test all memory locations in the partially-tested memory chips on the memory modules. Tests are performed at corner conditions such as high temperature and voltage. Infant mortality and single-bit faults are detected by the functional tests after module burn-in. The number of insertions into burn-in boards is reduced by the number of memory chips per module minus one, so handling and test costs are reduced.