Reduced-Height Memory Module With Cavity for SOC Die Nesting
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Solution Overview
Problem
Conventional memory systems have a high Z-height due to the placement of System on Chip (SOC) and DRAM dies on opposite sides of the substrate, which limits the compactness and efficiency of computing devices.
Innovation Solution
A memory system design where a DRAM die is positioned on the bottom of a substrate with wire bonds connecting it to the substrate, encapsulated by a molded layer with a cavity to accommodate a SOC die, and filled vias for conductive solder connections, reducing the Z-height by positioning both dies between the substrate and the SOC package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOC and DRAM dies are placed on opposite sides of the substrate, then electrical connections can be established between the dies, but the package Z-height increases
Solution Approach 1:
The patent places the DRAM die inside a cavity of the encapsulant layer, effectively nesting one die within the structure of another. This allows both the SOC die and DRAM die to coexist in a compact vertical arrangement, reducing the overall Z-height while maintaining electrical connectivity through wire bonds and solder connections.
Solution Approach 2:
Instead of strictly separating components on opposite sides of a substrate (two-dimensional arrangement), the patent utilizes the vertical dimension by creating a cavity within the encapsulant layer. This three-dimensional configuration allows the DRAM die to be positioned below the SOC die level, reducing Z-height while preserving all necessary electrical connections.
2Area of stationary object
If both DRAM and SOC dies are positioned between the substrate and SOC package, then space utilization improves, but the encapsulant layer structure becomes more complex
Solution Approach 1:
The encapsulant layer is segmented to include a specific cavity region that accommodates the DRAM die. This segmentation allows the encapsulant to serve dual purposes: protecting the SOC die and providing a structured housing for the DRAM die, thereby managing complexity through functional division rather than creating entirely separate structures.
Solution Approach 2:
The encapsulant layer is designed to perform multiple functions simultaneously: it encapsulates the SOC die, provides structural support, creates a cavity for the DRAM die, and facilitates thermal management. This multi-functionality reduces the need for additional separate components, improving space utilization without proportionally increasing overall system complexity.
Data Source
AI summary
A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.