Memory Module Defect Mapping via SPD-EEPROM
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Solution Overview
Problem
The existing manufacturing process for memory modules is inefficient in utilizing partially-good DRAM chips, as it involves costly and time-consuming individual testing and burn-in procedures, leading to wastage and high production costs.
Innovation Solution
A method is introduced where partially-good DRAM chips are initially tested and soldered onto memory module substrates, with defect maps programmed into SPD-EEPROM, allowing for parallel testing and burn-in of assembled memory modules, reducing testing time and costs by using lower-cost testers and simplifying the insertion/removal process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual testing and burn-in procedures are performed on each partially-good DRAM chip before assembly, then the reliability of memory modules is improved, but the manufacturing cost and time consumption increase significantly
Solution Approach 1:
The patent performs preliminary testing and defect mapping on DRAM chips at the wafer sort stage before packaging, creating defect maps that are stored in SPD-EEPROM. This preliminary action identifies defective locations in advance, allowing the system to work around defects rather than requiring exhaustive post-assembly testing, thus improving reliability while maintaining manufacturing efficiency.
Solution Approach 2:
The patent segments the memory module testing process into two phases: (1) individual chip defect mapping at wafer sort with defect tables stored in SPD-EEPROM, and (2) parallel functional testing of assembled modules using lower-cost testers that leverage the pre-stored defect information. This segmentation allows reliable testing without requiring expensive individual chip burn-in procedures.
2Manufacturing precision
If exhaustive testing is performed on packaged DRAM chips to identify all defects, then the quality of memory modules is improved, but the testing time and cost increase dramatically
Solution Approach 1:
The system performs preliminary defect identification at wafer sort using probe cards, creating defect maps that are stored in SPD-EEPROM on the memory module. This preliminary defect detection captures the majority of defects before packaging, eliminating the need for exhaustive post-assembly testing and significantly reducing testing time while maintaining high defect detection accuracy.
Solution Approach 2:
The patent introduces SPD-EEPROM as an intermediary that stores defect maps and configuration information. This intermediary allows the testing system to access pre-captured defect information without requiring physical re-testing of individual chips, thus reducing testing time while maintaining accurate defect identification.
3Reliability
If defective DRAM chips are discarded rather than utilized, then the reliability of memory modules is improved, but the production yield and cost efficiency deteriorate
Solution Approach 1:
The patent converts the harm of defective DRAM chips into a benefit by using defect maps stored in SPD-EEPROM to identify and work around defective locations. The system remaps good memory locations to replace defective ones, allowing partially-good chips to be utilized in memory modules. This approach maintains reliability by ensuring only functional memory locations are used while significantly improving production yield by salvaging chips that would otherwise be discarded.
Solution Approach 2:
The patent changes the operational parameters of the memory module by implementing remapping logic that dynamically adjusts memory address mappings based on defect information in SPD-EEPROM. This parameter change allows the system to accommodate defective chips by redirecting access to good memory locations, thereby utilizing partially-good DRAM chips while maintaining the required reliability standards.
4Measurement precision
If expensive automated test equipment is used for individual chip testing, then the measurement precision of defects is improved, but the manufacturing cost increases
Solution Approach 1:
The patent performs high-precision defect detection at wafer sort using probe cards before packaging, when chips are still on the wafer. This preliminary high-precision testing captures defect information that is then stored in SPD-EEPROM, eliminating the need for expensive automated test equipment during subsequent assembly and testing phases, thus reducing manufacturing costs while maintaining high measurement precision.
Solution Approach 2:
The patent creates a digital copy of the defect map in SPD-EEPROM that replicates the physical defect information. This copy allows lower-cost testers to access and utilize the high-precision defect data without requiring the expensive test equipment used during wafer sort, thereby maintaining measurement precision while reducing manufacturing costs.
Data Source
AI summary
A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability.