Memory Module Defragmentation for Low-Power Standby
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face increased power consumption and operation time due to the need to re-stabilize peripheral circuits when switching from standby to active mode, as power is removed during standby to reduce consumption but results in slower performance.
Innovation Solution
A memory module and system that perform defragmentation operations during low-power mode entry, update page tables, and power off vacant memory regions in self-refresh mode to minimize power usage, including a power controller, defragmentation controller, and power mode controller to manage power supply and refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power is removed from peripheral circuits during standby mode to reduce power consumption, then power consumption is reduced, but the operating speed is inevitably decreased
Solution Approach 1:
The patent performs defragmentation operations and updates page tables before entering standby mode, so that memory data is reorganized and peripheral circuits remain stable. This preliminary action avoids the need to re-stabilize circuits after mode switching, thus maintaining operating speed while reducing power consumption during standby
2Use of energy by moving object
If power is removed from peripheral circuits during standby mode, then power consumption is reduced, but the operation time increases due to re-stabilization required when switching to active mode
Solution Approach 1:
The system performs defragmentation and page table updates before entering standby mode, preparing memory in advance so that no additional time is required for re-stabilization when transitioning back to active mode. This eliminates the time penalty associated with circuit re-stabilization
3Use of energy by moving object
If defragmentation operation is performed during low-power mode entry, then power consumption is reduced and response time is enhanced, but the device complexity increases due to additional controllers and coordination
Solution Approach 1:
The power controller is designed to perform multiple functions: managing power supply to memory devices, controlling defragmentation operations, updating page tables, and coordinating mode transitions. By making the power controller multi-functional, the patent reduces the need for separate dedicated controllers, thus limiting the increase in device complexity while achieving power consumption reduction
Data Source
AI summary
In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.