Memory Module Dual Address Bus Parallel Read Latency
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Solution Overview
Problem
Current memory modules with non-volatile semiconductor storage, such as ReRAM, face challenges in achieving high reading speeds comparable to DRAM, particularly in addressing the latency issues associated with address conversion and input processes.
Innovation Solution
A memory module design that includes a non-volatile memory with dual address bus terminals and a controller that converts logical addresses into physical addresses using address lookup information, allowing simultaneous input of Row and Column addresses through separate bus terminals, thereby reducing read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If address conversion and address input are performed sequentially using a single address bus terminal, then device complexity is reduced, but reading speed deteriorates due to increased read latency
Solution Approach 1:
The address input process is segmented into two independent parts: row address input and column address input. Each part uses a separate address bus terminal, allowing parallel processing of address conversion and input operations, thereby reducing read latency while maintaining manageable device complexity through functional division
Solution Approach 2:
The system transitions from a single-dimensional sequential address input to a two-dimensional parallel address input structure. By introducing a second address bus terminal for column addresses while maintaining the first for row addresses, the system enables simultaneous address conversion and input operations in different dimensional spaces, improving reading speed without proportionally increasing complexity
2Loss of time
If dual address bus terminals are provided for parallel address input, then reading speed is improved by reducing read latency, but device complexity increases
Solution Approach 1:
The row address conversion and input is performed as a preliminary action before column address processing. By completing the first address conversion and input through the first bus terminal in advance, the system prepares the memory access state beforehand, allowing the second address bus terminal to handle column addresses without waiting, thereby reducing overall read latency while managing complexity through staged processing
Data Source
AI summary
Provided is a memory module which includes a controller which, upon reception of a read command including a logical address, converts the logical address included in the read command into a physical address using address lookup information. The controller further inputs a first physical address, which is a portion of the physical address obtained by the conversion, to a non-volatile memory via a first address bus terminal, and then inputs a second physical address, which is a rest of the physical address obtained by the conversion, to the non-volatile memory via a second address bus terminal, to thereby read data corresponding to the physical address obtained by the conversion from the non-volatile memory.