Multi-Rank Memory Module ECC Layout for Signal Integrity
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Solution Overview
Problem
Existing memory modules lack effective error correction capabilities with enhanced signal integrity, particularly in multi-rank configurations where data bus lines connect memory chips, leading to potential signal deterioration and errors during read/write operations.
Innovation Solution
Incorporating a stacked error correction code memory device with multiple error correction code memory chips, each connected via data bus lines to memory chips within specific ranks, enhancing error correction capabilities and signal integrity by using an Advanced Memory Buffer to compensate for signal deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are arranged in multiple ranks to increase memory capacity, then memory capacity increases, but signal integrity deteriorates due to longer data bus lines
Solution Approach 1:
The patent segments the error correction function into multiple independent ECC chips, each dedicated to a specific memory rank. This segmentation allows for localized error correction processing, reducing the signal transmission distance and improving signal integrity while maintaining the ability to handle multiple ranks of memory chips.
Solution Approach 2:
The patent introduces Advanced Memory Buffer (AMB) devices as intermediaries between the memory chips and the memory controller. These buffers compensate for signal deterioration by regenerating and retransmitting signals, effectively mediating the signal integrity issue that arises from using multiple memory chips across multiple ranks.
2Reliability
If error correction code memory chips are added to each rank to enhance error correction capabilities, then error correction capability improves, but device complexity increases
Solution Approach 1:
The patent merges the error correction functionality into the existing memory module structure by integrating ECC chips alongside the memory chips in a unified stacked configuration. This merging approach provides comprehensive error correction coverage across all memory ranks while maintaining a compact, organized device structure that does not significantly increase overall complexity.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture, placing ECC chips vertically above or below memory chips. This dimensional change allows for dense integration of error correction components without increasing the footprint area, thereby providing robust error correction capabilities while controlling device complexity.
3Ease of operation
If data bus lines connect memory chips across multiple ranks to enable data transfer, then memory accessibility improves, but signal deterioration occurs leading to errors
Solution Approach 1:
The patent implements preliminary error correction by placing ECC chips in close proximity to memory chips within each rank, enabling local error detection and correction before data is transmitted over long bus lines to the memory controller. This preliminary action prevents signal-related errors from propagating through the system.
Solution Approach 2:
The Advanced Memory Buffer devices serve as signal intermediaries that receive data from memory chips, compensate for signal deterioration through buffering and signal regeneration, and then forward the restored signals to the memory controller. This intermediary function maintains signal quality throughout the data transfer process across multiple ranks.
Data Source
AI summary
A memory module includes a plurality of memory devices and a stacked error correction code memory device. The plurality of memory devices includes one or more memory chips arranged in a plurality of ranks. The stacked error correction code memory device includes a plurality of error correction code memory chips. The number of error correction code memory chips is at least one more than the number of the one or more memory chips. Each of the error correction code memory chips are arranged together with the memory chips of one of the ranks.