Memory Module ECC Pooling for Limited Parity Bits
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in error correction capabilities due to the restricted number of parity bits, which hinders the detection and correction of errors as memory processes shrink and data fidelity requirements increase, necessitating a solution to enhance error detection and correction without increasing the number of memory cells.
Innovation Solution
Implementing a module-level error correction code (ECC) circuit that pools data and parity bits from multiple memory devices, allowing for increased error detection and correction capabilities by using additional parity bits across the module, and incorporating features like multilevel signaling and subdividing data and parity to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory devices use traditional ECC circuits with limited parity bits, then the device complexity remains low, but the error detection and correction capability is insufficient
Solution Approach 1:
The patent combines multiple memory devices into a module-level ECC system where parity bits from multiple devices are pooled together. This merging approach allows the system to achieve enhanced error detection and correction capabilities by treating the entire module as a single error correction unit, rather than having separate ECC circuits for each device.
Solution Approach 2:
The patent transitions from device-level error correction to module-level error correction, adding a new dimension to the ECC architecture. By operating at the module level rather than the individual device level, the system can utilize additional parity bits across multiple devices without proportionally increasing the complexity of each individual device's ECC circuit.
2Quantity of substance
If memory processes are shrunk to increase capacity, then the memory density improves, but the error detection and correction capability deteriorates due to restricted parity bits
Solution Approach 1:
The patent segments the error correction function across multiple memory devices within a module. Instead of concentrating all error correction resources in each individual device, the system divides the parity bit resources across multiple devices and combines them at the module level, allowing each device to maintain simple ECC circuits while the aggregate system achieves high error correction capability.
3Reliability
If additional parity bits are used to enhance error correction, then the error detection and correction capability improves, but the memory capacity decreases
Solution Approach 1:
The patent merges the parity bit resources from multiple memory devices to create a pooled error correction capability. This approach allows the system to achieve enhanced error correction without sacrificing the capacity of individual memory devices, as the additional redundancy is obtained by combining resources across the module rather than dedicating extra bits within each device.
4Reliability
If module-level ECC circuit pools data from multiple memory devices, then the error detection and correction capability improves, but the latency increases
Solution Approach 1:
The patent implements preliminary error correction actions at the module level by pooling and processing parity bits from multiple devices in parallel. This approach allows the system to perform error detection and correction on aggregated data without requiring sequential processing, thereby reducing the overall latency compared to traditional device-level ECC approaches.
Data Source
AI summary
Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.