Memory Module EDC Architecture for Low-Latency Error Correction
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Solution Overview
Problem
Existing DRAM modules face challenges in efficiently and economically correcting soft errors, as memory controllers with error-correction capabilities are expensive and can introduce significant read and write delays.
Innovation Solution
Incorporating error-detection and correction (EDC) components within the memory module to distribute error-correction logic among physically distributed components, using Hamming codes for error detection and correction, and optimizing syndrome bit usage to reduce the number of components and interconnection distances, thereby minimizing delays and maintaining high memory speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed in the memory controller, then error correction capability is provided, but the memory controller becomes expensive and introduces significant read and write delays
Solution Approach 1:
The patent segments the error correction function by distributing EDC components across multiple memory modules. Each memory module contains its own EDC components that independently perform error detection and correction for local memory components, eliminating the need for centralized error correction processing in the memory controller and thereby reducing read and write delays.
Solution Approach 2:
The patent moves the error correction functionality from the controller dimension to the module dimension by integrating EDC components directly into memory modules. This dimensional shift allows error correction to occur locally at the module level rather than requiring data to travel to and from the controller, significantly reducing processing time and delays.
2Loss of time
If EDC components are distributed among memory modules, then read and write delays are reduced, but the device complexity increases
Solution Approach 1:
The patent merges the EDC functionality with existing memory module components by integrating error detection and correction logic into the memory module's existing data paths. This integration approach allows error correction to be performed using existing module resources without requiring completely separate dedicated error correction hardware, thereby limiting the increase in device complexity.
3Measurement precision
If syndrome bits are stored in separate memory components, then error correction accuracy is improved, but the number of components and interconnection distances increase
Solution Approach 1:
The patent makes memory components universal by enabling them to serve dual functions: storing both data bits and syndrome bits. This multi-functionality allows the same physical memory resources to be used for both data storage and error correction information storage, eliminating the need for separate dedicated syndrome storage components and reducing overall device complexity.
Data Source
AI summary
A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.