Memory Module ECC Layout for Row and Column Error Correction
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Solution Overview
Problem
Existing memory modules struggle to effectively detect and correct both row direction errors and column direction errors, which can lead to system errors in external host devices.
Innovation Solution
A memory module configuration that includes multiple first memory chips for storing raw data and a second memory chip for storing parity data, using a combination of Reed-Solomon (RS) and single error correction double error detection (SECDED) error correction methods to detect and correct errors in both row and column directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single error correction method (e.g., SECDED) is used, then the structure is simple, but both row direction errors and column direction errors cannot be effectively detected and corrected
Solution Approach 1:
The error correction capability is segmented into two independent parts: first, SECDED parity bits are generated and stored; second, RS parity bits are generated and stored. Each segment handles specific error types, with SECDED addressing row direction errors and RS addressing column direction errors, thereby achieving comprehensive error correction without requiring a completely new unified structure
Solution Approach 2:
The patent combines two different error correction methods (SECDED and RS) into a composite error correction system. This composite approach leverages the strengths of both methods: SECDED provides efficient single error correction and double error detection, while RS provides robust correction for column direction errors, creating a more reliable overall system than either method alone
2Reliability
If only SECDED is used for error correction, then the correction speed is fast for single errors, but column direction errors cannot be corrected
Solution Approach 1:
The patent introduces RS parity bits as an intermediary layer that works in conjunction with SECDED. The RS parity bits specifically mediate the correction of column direction errors that SECDED cannot handle, while SECDED continues to handle row direction errors, creating a coordinated two-layer error correction system
3Reliability
If existing memory modules use traditional error correction, then the implementation is simple, but system errors cannot be prevented when both row and column errors occur
Solution Approach 1:
The patent performs preliminary error correction by pre-generating and storing both SECDED parity bits and RS parity bits with the data. This preliminary preparation enables the system to detect and correct both row and column direction errors before they cause system errors, preventing failures in advance rather than reacting to them
Data Source
AI summary
A memory module includes a plurality of first memory chips and a second memory chip. Raw data is stored in the plurality of first memory chips. Parity data generated based on the raw data is stored in the second memory chip. Each of the first memory chips and the second memory chip is configured to exchange data with a controller based on a burst length unit. The second memory chip stores a first parity data generated from the raw data by a first error correction method, and stores a second parity data generated from the raw data and the first parity data by a second error correction method.