Memory Module Error Information Path via Segmentation

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Solution Overview

Problem

In memory system architectures, error correction performed before data reaches the memory controller prevents the system from utilizing error information for operational decisions, limiting system management capabilities.

Innovation Solution

A memory module with a module error interface and device error interfaces allows for the communication of error information, enabling the controller to receive and respond to error information from memory devices, even if error correction occurs within the memory module.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction is performed before data is received by the memory controller, then error correction capability is improved, but error information availability to the system deteriorates

Engineering Contradiction:
Improveerror correction capabilityVSAvoiderror information availability
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent divides the communication path into two separate channels: a data path for transmitting corrected data and an error information path for transmitting error status. This segmentation allows error correction to occur while preserving error information through dedicated error information interfaces (device error interface and module error interface), resolving the contradiction between error correction capability and error information availability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediary error information interfaces that act as mediators between the memory devices and the system. These interfaces (device error interface and module error interface) capture and transmit error information separately from the data path, enabling the system to receive both corrected data and error status without interference, thus maintaining both error correction capability and error information availability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of information

If processor-based error correction is used, then error information availability is improved, but system cost and power consumption worsen

Engineering Contradiction:
Improveerror information availabilityVSAvoidsystem cost
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The patent implements self-service error correction at the memory device level, where memory devices perform their own error correction and generate error information. This eliminates the need for expensive processor-based error correction while maintaining error information availability through the dedicated error information interfaces, thereby reducing system cost and power consumption while preserving error information.

Inventive Principle:
Principle #25Self-service

3Loss of information

If processor-based error correction is used, then error information availability is improved, but power consumption worsens

Engineering Contradiction:
Improveerror information availabilityVSAvoidpower consumption
Core Design Contradiction:
Loss of informationVSUse of energy by moving object

Solution Approach 1:

The patent implements self-service error correction at the memory device level, where memory devices perform their own error correction and generate error information. This eliminates the need for power-consuming processor-based error correction while maintaining error information availability through the dedicated error information interfaces, thereby reducing system power consumption while preserving error information.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10824499B2Memory system architectures using a separate system control path or channel for processing error information
Publication Date: 2020.11.03 SAMSUNG ELECTRONICS CO LTD
  • US10824499B2 patent drawing
  • US10824499B2 patent drawing
  • US10824499B2 patent drawing

AI summary

An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.