Memory Module Extra Regions Bypass DRAM Errors
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Solution Overview
Problem
In memory systems using multiple DRAMs, when an error occurs in one DRAM, the remaining DRAMs in the same rank cannot perform normal write/read operations, leading to a demand for a method to effectively process data from error-occurred DRAMs.
Innovation Solution
A memory system and operation method that utilize extra memory regions in other memory modules to redirect and process data intended for error-occurred DRAMs, allowing parallel data processing by generating and using alternative commands/addresses to write/read data from these extra regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DRAMs are accessed in parallel to increase operation speed, then productivity is improved, but reliability deteriorates because an error in one DRAM causes failure of the entire rank
Solution Approach 1:
The patent segments the memory system into multiple ranks, where each rank is an independent operational unit. When an error occurs in one DRAM within a rank, only that specific DRAM is affected, while other ranks continue to operate normally. This segmentation isolates the error impact and prevents cascading failures across the entire memory system, thereby maintaining reliability while preserving parallel access capability across multiple ranks.
2Reliability
If an error-occurred DRAM is processed as a failure, then reliability is improved by preventing error propagation, but productivity deteriorates because remaining DRAMs in the same rank cannot perform operations
Solution Approach 1:
The patent applies local quality by implementing error handling at the DRAM-level rather than rank-level. Each DRAM is independently monitored and managed, allowing the system to identify and isolate errors to specific defective cells while maintaining operational capability of other DRAMs within the same rank. This localized error management preserves the operational capacity of healthy memory elements.
Solution Approach 2:
The patent introduces a new dimension of error management by implementing cross-rank data redirection capability. When a DRAM error is detected, the system can redirect data operations from the affected DRAM to alternative DRAMs in different ranks, effectively adding a spatial dimension to error recovery. This allows the system to maintain productivity by utilizing memory resources across multiple ranks rather than being confined to the original rank structure.
3Quantity of substance
If the number of DRAMs in one memory module is increased to satisfy larger memory capacity, then quantity of substance is improved, but device complexity increases making error management more difficult
Solution Approach 1:
The patent implements universal error management mechanisms that function consistently across all ranks and DRAMs regardless of the total number of memory devices. The error detection, isolation, and redirection protocols are designed to be rank-agnostic and scalable, allowing the same error handling framework to manage systems with varying numbers of DRAMs without increasing operational complexity. This universal approach enables the system to accommodate larger memory capacities while maintaining manageable error handling procedures.
Data Source
AI summary
A memory module may include a first memory module comprising a plurality of first memory devices each having an extra memory region, a second memory module comprising a plurality of second memory devices each having an extra memory region, and a control logic suitable for writing/reading data to/from the first memory devices, wherein the control logic writes/reads target data to be transferred to/from a third memory device having an error among the first memory devices, to/from the extra memory regions of the second memory devices.