Memory Module Clock and Power Fault Detection Circuit

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Solution Overview

Problem

Volatile memory modules lose data when power is interrupted, and existing systems lack efficient methods to maintain data integrity during power failures or clock malfunctions, necessitating a solution for fault detection and backup power management within the memory module.

Innovation Solution

A system comprising a voltage detection circuit, clock detection circuit, controller, memory control state machine, and battery regulation circuitry within a unitary memory module, which detects voltage and clock signals, initiates backup operations, and maintains memory through refresh, allowing the module to operate in a backup mode during power failures or clock malfunctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If volatile memory is used to provide fast storage, then speed is improved, but data loss occurs when power is interrupted

Engineering Contradiction:

Improvememory access speedVSAvoiddata retention during power failure

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The system performs preliminary actions by detecting power failures or clock malfunctions before data is lost, then initiates backup operations to transfer critical data to non-volatile storage. The voltage detection circuit and clock detection circuit continuously monitor system conditions and trigger backup procedures in advance of complete data loss.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary components including a voltage detection circuit, clock detection circuit, and controller that act as mediators between the volatile memory and non-volatile storage. These intermediaries detect faults and coordinate data transfer operations to preserve data integrity during power interruptions or clock failures.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If non-volatile memory is used to retain data during power loss, then data retention is improved, but access speed deteriorates

Engineering Contradiction:

Improvedata retention during power failureVSAvoidmemory access speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The system maintains data in fast volatile memory during normal operation and only transfers to non-volatile storage when a power failure or clock malfunction is detected. This preliminary monitoring approach allows the system to use high-speed memory for routine operations while having a ready backup mechanism activated only when needed.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Rather than continuously copying all data between volatile and non-volatile memory, the system performs partial action by transferring only critical data that needs preservation during fault conditions. The selective backup approach maintains speed performance for normal operations while providing protection for essential information.

Inventive Principle:

Principle #16Partial or excessive action

3Difficulty of detecting and measuring

If external system circuitry is used for fault detection, then detection capability is improved, but device complexity increases

Engineering Contradiction:

Improvefault detection capabilityVSAvoidexternal circuitry requirements

Core Design Contradiction:

Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent merges the voltage detection circuit, clock detection circuit, controller, and state machine into a single integrated memory module. This consolidation provides comprehensive fault detection capability while reducing external circuitry requirements, as the detection functions are now self-contained within the module rather than requiring separate external components.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory module performs self-service by incorporating its own voltage detection, clock detection, and fault response capabilities. The module autonomously monitors its operating conditions and executes backup operations without requiring complex external control circuitry, thereby simplifying the overall system architecture while maintaining robust fault detection.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS8644105B2Clock and power fault detection for memory modules

Publication Date: 2014.02.04 BARCLAYS BANK PLC AS SUCCESSOR AGENT

AI summary

A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.