Memory Module Integrating Processor for High Throughput

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Solution Overview

Problem

Current PCIe interfaces are bottlenecked by their lower data throughput compared to DDR4/5 memory interfaces, which limits the performance of AI and GPU applications.

Innovation Solution

A memory module that allows a CPU to access processed results from a processor, such as an FPGA, via a DDR interface, reducing latency and increasing data throughput between the CPU and the processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If PCIe interface is used to connect processor to CPU, then device compatibility and standard interface usage are maintained, but data throughput is limited and latency is high

Engineering Contradiction:

Improvedata throughputVSAvoidinterface complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent merges the processor (FPGA/GPU) directly with the memory module to create an integrated unit that connects to the CPU via DDR memory interface. This combining of processing and memory functions eliminates the need for separate PCIe interface infrastructure, enabling direct high-speed access to memory while maintaining standard memory interface compatibility.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory module is designed to serve multiple functions: it acts as both memory storage and as a communication interface between the processor and CPU. By making the memory module universal (capable of both storage and high-speed data transfer), the system eliminates the need for dedicated PCIe interfaces while maintaining standard interface compatibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If PCIe interface is used for AI applications, then standard communication protocol is maintained, but data throughput becomes a bottleneck limiting AI performance

Engineering Contradiction:

ImproveAI processing performanceVSAvoiddata throughput

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

The processor is merged directly with the memory module, creating an integrated unit that bypasses the PCIe interface bottleneck. This allows AI applications to access memory and process data at much higher speeds through the DDR memory interface, directly improving AI processing performance without being constrained by PCIe throughput limitations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory module acts as an intermediary between the processor and CPU, providing a high-speed data pathway that eliminates the PCIe bottleneck. By routing data through the memory interface rather than PCIe, the system achieves the high throughput necessary for demanding AI workloads while maintaining standard interface compatibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250036317A1Memory module and computing device containing the memory module

Publication Date: 2025.01.30 AI PLUS INC

AI summary

Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the processor to communicate with the one or more DRAMs via a memory interface.