Memory Module Mirroring Circuit for Symmetric Address Routing
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Solution Overview
Problem
Existing memory modules face challenges in efficiently transmitting address signals due to limitations in reducing cell size, which hinders the implementation of high-capacity DRAMs within a limited area.
Innovation Solution
A memory module design with symmetric transmission lines and selective address mirroring circuits, where groups of semiconductor memory devices are disposed symmetrically on a circuit board and operate in mirrored or standard modes based on voltage levels, allowing efficient address signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DRAMs are provided in a memory module to achieve high capacity, then storage capacity is improved, but address signal transmission efficiency deteriorates
Solution Approach 1:
The memory module is divided into multiple groups of semiconductor memory devices, with each group disposed between the control device and different edge portions of the circuit board. This segmentation allows address signals to be transmitted to multiple memory devices simultaneously through separate transmission lines, improving transmission efficiency while maintaining high capacity
Solution Approach 2:
The patent introduces physical symmetry in the transmission line configuration, where the first and second transmission lines are arranged symmetrically with respect to the control device. This symmetric arrangement optimizes signal transmission characteristics and reduces interference, thereby improving address signal transmission efficiency in high-capacity memory modules
2Area of stationary object
If DRAM cell size is reduced to fit within limited area, then area utilization is improved, but cell size reduction is limited by structural constraints
Solution Approach 1:
The patent transitions from a single-dimensional memory arrangement to a multi-dimensional layout by disposing memory device groups in different spatial regions between the control device and edge portions. This dimensional expansion allows high-capacity memory implementation within limited area constraints
3Productivity
If semiconductor memory devices are disposed symmetrically on circuit board, then address signal transmission efficiency is improved, but device arrangement complexity increases
Solution Approach 1:
The patent employs symmetric arrangement of transmission lines and memory device groups relative to the control device. This symmetry simplifies signal routing and reduces interference, improving address signal transmission efficiency while the modular group structure keeps the overall arrangement manageable
Data Source
AI summary
A memory module is provided including a plurality of semiconductor memory devices mounted on a circuit board. A control device is mounted on the circuit board and configured to receive a command signal, an address signal, and a clock signal and to provide the command signal, the address signal, and the clock signal to the plurality of semiconductor memory devices. A first group of the semiconductor memory devices is disposed between the control device and a first edge portion of the circuit board, and a second group of the semiconductor memory devices is disposed between the control device and a second edge portion of the circuit board. The control device is configured to transmit the address signal to the first group of the semiconductor memory devices and the second group of the semiconductor memory devices through a first transmission line and a second transmission line, respectively. The first transmission line and the second transmission line are physically symmetric with respect to an axis intersecting the control device.