Controller-Free Memory Module Native Interface Heat Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing memory capacity of non-volatile random access memory modules leads to heat dissipation issues due to controllers managing numerous memory chips, and existing modules require interface conversion from native to DDR interfaces, necessitating additional space and power supply for volatile memory chips.
Innovation Solution
A memory module without a controller or built-in power supply, where the motherboard's integrated memory controller accesses non-volatile memory chips via their native interfaces, reducing the need for interface conversion and accommodating more memory chips by eliminating the need for DDR interface conversion and volatile memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If controllers are integrated on non-volatile random access memory modules to manage multiple memory chips, then memory capacity is increased, but heat dissipation problems occur due to the controllers managing a great number of memory chips
Solution Approach 1:
The controller is extracted from the memory module and relocated to the motherboard. This separation removes the heat-generating controller from the memory module, allowing the module to accommodate more memory chips without suffering from heat dissipation problems caused by the controller's operations.
Solution Approach 2:
Multiple memory modules are merged under a single controller on the motherboard. Instead of each memory module having its own controller, one controller manages multiple modules, reducing the total number of controllers and thereby reducing overall heat generation while supporting increased memory capacity.
2Adaptability or versatility
If controllers on non-volatile random access memory modules perform interface conversion from native to DDR interfaces, then compatibility with motherboard is achieved, but device complexity increases due to additional conversion operations
Solution Approach 1:
The interface conversion function is extracted from the memory module controller and relocated to the motherboard's memory controller. This allows the memory module to use its simple native interface without needing to perform complex conversion operations, reducing device complexity while maintaining compatibility through the motherboard's conversion capability.
Solution Approach 2:
The motherboard's memory controller acts as an intermediary that handles the interface conversion between the memory module's native interface and the DDR interface required by the system. This mediator approach eliminates the need for complex conversion circuits within the memory module itself.
3Ease of operation
If volatile memory chips are used in non-volatile random access memory modules, then operation management is enabled, but power consumption increases due to the need for built-in power supply
Solution Approach 1:
The volatile memory chips and their associated power supply requirements are extracted from the non-volatile memory module. The module uses only non-volatile memory chips that do not require continuous power supply, eliminating the need for built-in power supply circuits and significantly reducing power consumption while maintaining operation management capabilities through the motherboard's controller.
Data Source
AI summary
A memory module without a controller and without a built-in power supply and a memory controller thereof are provided. The memory module includes a connection portion, a first non-volatile memory chip, and a second non-volatile memory chip. The memory controller of the motherboard accesses the first non-volatile memory chip by a native interface of the first non-volatile memory chip through the connection portion. The second non-volatile memory chip is configured to store at least one pointer of a meta data of the first non-volatile memory chip. The memory type of the second non-volatile memory chip is different from the memory type of the first non-volatile memory chip. The memory controller accesses the pointer stored in the second non-volatile memory chip through the connection portion.