Memory Module On-Die Termination Signal Integrity
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Solution Overview
Problem
Existing memory modules face challenges in maintaining signal integrity due to impedance mismatch, leading to inter symbol interference, which is exacerbated by the use of stub series terminated logic (SSTL) methods in multi-drop bus structures like SDRAM, DDR1 SDRAM, DDR2 SDRAM, and DDR3 SDRAM, resulting in reduced signal reliability and increased production costs.
Innovation Solution
The implementation of a memory system with a printed circuit board (PCB) where memory devices are arranged in rows with varying distances from connection terminals, with some signal lines connecting to stub resistors and others not, allowing for selective impedance matching through on-die termination (ODT) circuits to minimize signal reflections and maintain signal integrity without the need for stub resistors in all connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stub resistors are added to all signal lines to improve signal integrity, then signal reflection is reduced, but device complexity and production cost increase
Solution Approach 1:
The patent applies local quality by selectively placing stub resistors only on signal lines where impedance mismatch and signal reflection problems occur, rather than uniformly adding them to all signal lines. This targeted approach maintains signal integrity where needed while avoiding unnecessary complexity and cost in other areas of the memory module.
Solution Approach 2:
The patent changes the parameter of stub resistor placement from a uniform configuration to a selective configuration based on signal line characteristics. By adjusting which signal lines receive stub resistors based on their specific impedance matching needs, the system optimizes signal integrity while minimizing the total number of stub resistors required.
2Reliability
If stub resistors are added to all signal lines to reduce signal reflection, then signal integrity improves, but production cost increases
Solution Approach 1:
The patent implements local quality by identifying specific signal lines that require stub resistors for proper impedance matching, rather than adding them universally. This selective approach reduces the bill of materials cost and assembly complexity, directly lowering production costs while maintaining signal integrity for affected signal lines.
Solution Approach 2:
The patent treats stub resistors as selective components rather than universal ones, applying them only where economically justified by signal integrity requirements. This approach optimizes the cost-benefit ratio by eliminating unnecessary stub resistors that would increase production cost without providing corresponding value.
3Productivity
If memory devices are arranged in multi-drop bus structures to increase bandwidth, then data transmission capacity improves, but impedance mismatch and inter symbol interference increase
Solution Approach 1:
The patent addresses the signal integrity problems inherent in multi-drop bus structures by selectively applying stub resistors to specific signal lines within the bus architecture. This localized intervention maintains the high bandwidth capability of the multi-drop structure while correcting impedance mismatch and reducing inter symbol interference where they occur.
Solution Approach 2:
The patent uses stub resistors as intermediary components inserted at strategic points in the signal path to mediate between the high-speed multi-drop bus structure and the memory devices. These intermediaries provide impedance matching that reduces signal reflection and inter symbol interference, enabling the bus structure to operate at high speeds without sacrificing signal integrity.
Data Source
AI summary
A memory system includes a plurality of memory devices on a printed circuit board, each of the memory devices including a plurality of external pads; a plurality of connection terminals formed on the printed circuit board, and electrically connected to respective ones of the external pads; and a plurality of signal lines formed on the printed circuit board to connect the connection terminals with the external pads, each of the signal lines between a corresponding connection terminal and a corresponding external pad and having a length. The plurality of memory devices are arranged at different distances from the plurality of connection terminals, and each signal line that connects a connection terminal to an external pad of a memory device either is connected to or does not connect a stub resistor depending on a length of the line.