Memory Module Parity Storage in LSBs for Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor memory devices increase in operating speed, the probability of data errors also increases, leading to higher costs due to the need for additional memory chips to store parity codes for error correction, which complicates error detection and correction processes.
Innovation Solution
A memory module and system design that includes M memory chips for data storage and an additional (M+1)th chip for storing parity codes, with each memory chip equipped with an in-DRAM error correction circuit to generate fail bits for error detection and correction, allowing for data recovery without a separate detection code, thereby reducing manufacturing costs and improving error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory controller generates and stores parity codes in separate memory chips to correct errors, then error correction capability is improved, but the number of memory chips increases and manufacturing cost increases
Solution Approach 1:
The patent combines the parity code storage function with existing data memory chips. Specifically, the least significant bits (LSBs) of data stored in memory chips are used to store parity information instead of requiring separate dedicated parity chips. This merging approach allows the same memory resources to serve dual purposes: storing both data and error correction codes, thereby reducing the total number of memory chips needed while maintaining error correction capability
Solution Approach 2:
The patent makes memory chips universal by enabling them to perform multiple functions. Each memory chip not only stores data but also contributes to storing parity information through its LSBs. Additionally, the memory chips participate in both data retrieval and error detection/correction processes. This multi-functionality eliminates the need for specialized separate chips for parity storage, reducing overall system complexity and cost
2Reliability
If additional memory chips are added to store parity codes for error correction, then error detection and correction capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error detection and correction process with the normal data retrieval process. When data is read from memory chips, the same data bus and control logic are used to retrieve both data and parity information. The memory controller performs error checking by comparing retrieved data against stored parity bits using the existing data paths, eliminating the need for separate complex error detection hardware and simplifying the overall system architecture
Solution Approach 2:
The patent implements a self-service error correction mechanism where the memory system uses its own existing resources (data buses, control logic, and memory chips) to perform error detection and correction without requiring additional dedicated error handling subsystems. The parity information stored within the data chips themselves enables the system to self-diagnose and self-correct errors using its inherent operational pathways
Data Source
AI summary
A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.