Memory Module Read Training via Partial Data Pin Activation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAM systems require all data pins to be toggled during read training, leading to increased power consumption and inefficiency in timing calibration.
Innovation Solution
A memory module and controller system where the training signal is transmitted through only a portion of the data pins or a specific pin, reducing power consumption and enabling more frequent timing calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all data pins are toggled during read training to obtain timing information, then timing calibration accuracy is improved, but power consumption increases
Solution Approach 1:
The patent divides the data pins into multiple groups and assigns different group identifiers to each group. During read training, only one group of pins is activated at a time to transmit training signals, while other groups remain inactive. This segmentation allows timing calibration to be performed on subsets of pins rather than all pins simultaneously, reducing overall power consumption while maintaining calibration accuracy for each group.
Solution Approach 2:
The patent implements partial action by activating only a portion of the data pins (one group at a time) during read training operations instead of all data pins. The training signal is transmitted through selected pins identified by group identifiers, enabling timing calibration to be performed with partial pin activation, thereby reducing power consumption while still achieving the necessary timing information.
2Measurement precision
If all data pins are driven during read training, then complete timing information is obtained, but device complexity increases
Solution Approach 1:
The patent segments data pins into multiple groups with distinct group identifiers and implements corresponding receiving units in the memory controller. Each receiving unit is configured to receive training signals from specific pin groups. This segmentation organizes the complex training operation into manageable segments, reducing the overall device complexity while ensuring complete timing information is obtained across all pin groups through systematic sequential processing.
Solution Approach 2:
The patent applies partial action by performing read training operations on one pin group at a time rather than all pins simultaneously. The memory controller sequentially activates different pin groups identified by group identifiers, obtaining timing information from each group in turn. This approach reduces training operation complexity by breaking down the comprehensive training process into simpler, manageable partial operations.
Data Source
AI summary
A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.


