Memory Module Architecture Reducing Pin Count via Signal Repeaters
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Solution Overview
Problem
Conventional memory modules face challenges in achieving stable signal integrity and high data transfer rates due to capacitive loading issues when operating at high frequencies, particularly above 1 GHz, especially with the increasing number of pins required for differential signaling, which exceeds mechanical design limits in personal computers.
Innovation Solution
The implementation of a memory module architecture where command/address and data signals are transmitted through a common bus, with repeaters in each memory device redistributing these signals to adjacent devices, reducing the number of pins needed and mitigating capacitive loading effects by using point-to-point connections and data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential signaling is used to achieve high data transfer rates above 3,200 Mbps, then signal integrity is improved, but the number of pins required doubles to 128 data pins
Solution Approach 1:
The memory module divides memory devices into two sets: a first set directly coupled to the memory controller, and a second set coupled through memory devices in the first set. This segmentation allows the system to use fewer pins while maintaining high data transfer rates, as not all memory devices need direct differential signaling connections to the controller.
Solution Approach 2:
Memory devices in the first set act as intermediaries, receiving data from the memory controller and transmitting it to memory devices in the second set. This intermediary approach reduces the total number of pins required while maintaining signal integrity through controlled signal paths.
2Device complexity
If the number of memory devices is reduced to avoid design limits on pin count, then device complexity is reduced, but data throughput decreases
Solution Approach 1:
The patent introduces a hierarchical dimension to the memory architecture, organizing memory devices into multiple sets with different coupling configurations. This allows the system to maintain high data throughput by keeping many memory devices while reducing pin count through the hierarchical structure, rather than simply reducing the total number of devices.
3Quantity of substance
If conventional multi-drop configuration is used to reduce pin count, then device complexity is reduced, but capacitive loading increases at high operating frequencies
Solution Approach 1:
The patent applies different coupling configurations to different sets of memory devices based on their specific needs. The first set uses direct point-to-point connections for devices requiring high-speed access, while the second set uses connections through intermediaries for devices that can tolerate slightly longer paths. This local differentiation optimizes signal integrity for each device while managing overall pin count.
Data Source
AI summary
A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.