Memory Module Power Management with Buck Converters and Voltage Monitoring
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Solution Overview
Problem
Existing memory systems face inefficiencies in data transfer due to the disparity in access speeds between Flash and DRAM, leading to performance bottlenecks and reduced CPU efficiency, with volatile memory solutions requiring battery maintenance and environmental concerns.
Innovation Solution
A hybrid memory module integrating non-volatile Flash and volatile DRAM subsystems with a controller and data manager to optimize data transfer, manage data flow, and provide a unified memory space, reducing the impact of Flash access speed on overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If Flash memory is used for non-volatile storage, then data retention without power is improved, but data transfer speed deteriorates
Solution Approach 1:
The memory system is segmented into two distinct subsystems: a volatile DRAM subsystem for high-speed data access and a non-volatile Flash subsystem for data retention. This segmentation allows each subsystem to operate at its optimal performance level without compromising the other, resolving the contradiction between speed and data retention.
Solution Approach 2:
A controller acts as an intermediary between the DRAM and Flash subsystems, managing data transfer and caching operations. The controller optimizes the interaction between the fast DRAM and slower Flash, minimizing the impact of Flash access speed on overall system performance while maintaining data retention capabilities.
2Reliability
If battery-based power solution is used for volatile memory, then data protection during power failure is improved, but environmental harm and maintenance requirements worsen
Solution Approach 1:
The system uses a capacitor-based power solution instead of battery-based power management. The capacitor provides short-term power sustainment during power failures without the environmental harm, maintenance requirements, and reliability issues associated with batteries, while still protecting data integrity.
3Measurement precision
If CPU directly manages data transfer between storage and memory, then control precision is improved, but CPU efficiency and productivity worsen
Solution Approach 1:
A memory controller serves as an intermediary device between the CPU and the hybrid memory system, handling data transfer management between DRAM and Flash subsystems. This offloads the burden of direct CPU management, improving CPU efficiency while maintaining precise control over data transfer operations through the specialized controller.
Data Source
AI summary
In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.