Memory Module Cache Prefetching via Access Pattern Algorithms

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Solution Overview

Problem

Current memory modules lack efficient data prefetching and eviction strategies based on host access patterns, leading to suboptimal performance and resource utilization.

Innovation Solution

A memory module system that utilizes a CXL interface, incorporating a memory controller with cache memory, map management data storage, and prefetch controllers, which employ algorithms like temporal locality, spatial locality, branch locality, and sequential locality to prefetch and evict data based on access patterns, optimizing data placement across multiple memory tiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is prefetched based on host access patterns using multiple algorithms, then memory system performance is improved and latency is reduced, but device complexity increases due to the need for cache memory, map management data storage, and prefetch controllers

Engineering Contradiction:
Improvememory system performanceVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by prefetching data into cache memory before the host actually requests it. The prefetch controller predicts which data will be needed next based on access patterns stored in map management data storage, and pre-loads this data into cache memory, eliminating future wait time for data access.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces cache memory as an intermediary layer between the host and the main memory device. This intermediary buffer stores frequently accessed or predicted data, allowing the host to access data faster without directly querying the slower main memory, thus improving overall system performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If access pattern information is stored and multiple algorithms are used for prefetching, then data access efficiency is improved, but the use of energy increases due to additional processing and storage operations

Engineering Contradiction:
Improvedata access latencyVSAvoidenergy consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting prefetching behavior based on different access pattern characteristics. The system analyzes access patterns stored in map management data storage and modifies prefetching parameters such as prefetch size, prefetch timing, and algorithm selection to match the observed access behavior, optimizing the balance between reduced latency and energy consumption.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240385969A1Memory module, memory system including memory module, and method of operating the same
Publication Date: 2024.11.21 SK HYNIX INC
  • US20240385969A1 patent drawing
  • US20240385969A1 patent drawing
  • US20240385969A1 patent drawing

AI summary

The present technology relates to an electronic device. According to the present technology, a memory system includes a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface and having a tier lower than that of the first memory module. The first memory module comprises a memory device and a memory controller. The memory device may store cache data. The memory controller may store access pattern information of the host for the memory device, select candidate data to be evicted among the cache data based on the access pattern information of the host and a plurality of algorithms, and evict target data among the candidate data.