Memory Module Rank Segmentation for Speed

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Solution Overview

Problem

Contemporary memory systems face challenges in increasing data storage capacity without incurring deleterious rank loading effects that slow operating speed, particularly as the number of memory device ranks is expanded.

Innovation Solution

A memory module architecture where memory devices are grouped into two categories: a first grouping directly connected to the memory controller and a second grouping indirectly connected through the first grouping, allowing each memory device to selectively provide self-data or other-data during read operations, thereby distributing data transmission load efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of ranks arranged on the memory module is increased to expand data storage capacity, then data storage capacity is improved, but operating speed deteriorates due to rank loading effects

Engineering Contradiction:
Improvedata storage capacityVSAvoidoperating speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The patent divides memory devices into two distinct groupings: a first grouping directly connected to the memory controller, and a second grouping indirectly connected through the first grouping. This segmentation allows the memory controller to directly manage only the first rank's devices, reducing the loading effect impact on operating speed while still providing expanded data storage capacity through the additional second grouping devices.

Inventive Principle:
Principle #1Segmentation

2Speed

If memory devices are directly connected to the memory controller, then operating speed is maintained, but data storage capacity is limited by the number of directly connected devices

Engineering Contradiction:
Improveoperating speedVSAvoiddata storage capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The first grouping of memory devices acts as an intermediary between the memory controller and the second grouping of memory devices. The memory controller communicates with the first grouping directly, which then facilitates access to the second grouping indirectly. This intermediary structure enables expanded data storage capacity through the second grouping while maintaining operating speed by keeping the controller's direct connection load limited to the first grouping only.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9542343B2Memory modules with reduced rank loading and memory systems including same
Publication Date: 2017.01.10 SAMSUNG ELECTRONICS CO LTD
  • US9542343B2 patent drawing
  • US9542343B2 patent drawing
  • US9542343B2 patent drawing

AI summary

A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation.