Memory Module Buffer Repair for Recurring Hard Read Errors
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Solution Overview
Problem
Memory systems employing error codes face limitations in correcting multiple-bit errors, leading to premature failure of memory components when hard errors occur, especially during assembly and testing of memory modules.
Innovation Solution
Incorporating a buffer circuit with error logic and repair logic within the memory module to identify and repair storage cell failures, allowing for in-module error correction and maintaining the error correction capability, thereby preventing recurring hard errors and extending the life of memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error codes with redundancy are employed to detect and correct errors, then error detection capability is improved, but the overhead limits the code effectiveness to single-bit errors only
Solution Approach 1:
The patent segments the error correction function into two parts: (1) the existing error code at the memory controller for single-bit error correction, and (2) a separate buffer circuit with its own error detection logic and repair logic for handling multi-bit hard errors. This segmentation allows each component to specialize in different error types without increasing overall system overhead.
Solution Approach 2:
The buffer circuit acts as an intermediary between the memory device and the memory controller. It intercepts read data, performs additional error detection and repair operations, and only passes corrected data to the controller. This intermediary approach enables multi-bit error handling without requiring the main error correction code to be more complex.
2Manufacturing precision
If memory devices are assembled onto memory modules and subjected to final testing, then manufacturing quality is improved, but hard errors cause module failure and discarding
Solution Approach 1:
The buffer circuit performs preliminary error repair actions during the manufacturing testing phase. When hard errors are detected in storage cells during final testing, the repair logic identifies them and performs repair operations, storing repair information in non-volatile memory. This preliminary repair prevents modules with hard errors from being discarded.
Solution Approach 2:
The memory module performs self-diagnosis and self-repair through the buffer circuit's error detection and repair logic. During manufacturing testing, the buffer automatically detects hard errors in storage cells and repairs them without external intervention, allowing the module to pass final testing and be deployed reliably.
3Reliability
If in-module error repair capability is incorporated in the buffer circuit, then error correction effectiveness is improved, but changes to memory controller and device designs are required
Solution Approach 1:
The patent extracts the multi-bit error repair functionality from the memory controller and memory device designs, placing it entirely within the buffer circuit. The buffer contains the error detection logic, repair logic, and non-volatile memory for storing repair information, making the repair capability self-contained and independent of controller or device design changes.
4Device complexity
If hard errors are not repaired, then device simplicity is maintained, but recurring hard errors cause premature failure of memory components
Solution Approach 1:
The buffer circuit implements a feedback mechanism where error detection logic continuously monitors read data for hard errors. When errors are detected, the repair logic performs repair operations and stores the repair information in non-volatile memory. This feedback loop ensures that hard errors are automatically corrected, preventing premature failure and extending memory device lifespan without significantly increasing complexity.
Data Source
AI summary
A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.