Memory Module Ring Topology for Sequential Impedance Calibration
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Solution Overview
Problem
As semiconductor memory devices operate at increased speeds, signal distortion due to impedance mismatch caused by PVT variations becomes more pronounced, necessitating effective impedance calibration to prevent abnormal operation and ensure signal integrity.
Innovation Solution
A memory module and system that utilize an external resistor and a ring topology among memory devices to perform sequential impedance calibration, where one memory device acts as a master to calibrate its own impedance and then transfer the calibration command to adjacent devices, preventing overlapping calibration operations and ensuring accurate resistance and output voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If impedance calibration is performed in all memory devices simultaneously, then calibration speed is improved, but signal distortion and calibration accuracy deteriorate due to overlapping operations
Solution Approach 1:
The patent segments the simultaneous calibration process into sequential phases by designating one memory device as master and others as slaves. The master device performs calibration first, then transfers control to slave devices in sequence. This segmentation prevents overlapping calibration operations while maintaining systematic coverage of all memory devices, resolving the contradiction between calibration speed and accuracy.
Solution Approach 2:
The master memory device performs impedance calibration as a preliminary action before other slave devices begin their calibration. This preliminary execution ensures that the master device's calibration is complete and stable before subsequent devices start their processes, preventing signal interference and maintaining calibration accuracy across all devices.
2Loss of time
If multiple memory devices perform impedance calibration simultaneously, then overall calibration time is reduced, but signal integrity deteriorates due to PVT variations and impedance mismatch
Solution Approach 1:
The calibration process is segmented into sequential time slots assigned to different memory devices. The master device operates in the first time slot, followed by slave devices in subsequent slots. This temporal segmentation eliminates simultaneous operations that cause signal interference, ensuring signal integrity while completing calibration for all devices in a structured manner.
Solution Approach 2:
The patent implements periodic calibration action where each memory device performs calibration in its designated time period. The master device completes calibration first, then the system transitions to the next device in sequence. This periodic structure ensures that calibration operations are evenly distributed in time, preventing signal overlap and maintaining reliability.
3Productivity
If all memory devices are calibrated in parallel, then manufacturing productivity is improved, but calibration reliability deteriorates due to overlapping impedance adjustment operations
Solution Approach 1:
The parallel calibration approach is segmented into a coordinated sequential process. One memory device is designated as master and performs calibration first, establishing a reliable reference. Other devices follow in sequence as slaves, each completing calibration before the next begins. This segmentation maintains manufacturing productivity by systematically processing all devices while ensuring each calibration operation completes reliably without interference.
Solution Approach 2:
The master memory device acts as an intermediary that coordinates the calibration process across all devices. It performs calibration first, then facilitates the sequential calibration of slave devices. This intermediary role ensures that calibration operations are properly ordered and synchronized, maintaining both productivity and reliability by preventing overlapping operations while efficiently processing all memory devices.
Data Source
AI summary
A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.