Multi-Mode Memory Module Self-Testing at System Speed
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Solution Overview
Problem
Existing memory testing methodologies, particularly for DRAM, are costly and time-consuming due to the need for external test equipment and embedded self-test logic, which is not fully utilized for system-level testing, leading to increased system costs and decreased performance.
Innovation Solution
A self-testing memory module with a control and data module configuration that allows for internal testing without additional pins, utilizing JEDEC standard memory protocols and an I2C interface for configuration and result reading, enabling testing at target system speed and without external equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external test equipment (ATE) is used for memory testing, then testing completeness and reliability are improved, but system cost increases significantly
Solution Approach 1:
The memory module performs self-testing using built-in self-test logic (MBIST) that resides within the memory chip itself. The system memory controller initiates and controls the test, but the actual testing functionality is embedded in the memory device, eliminating the need for expensive external automatic test equipment (ATE). This self-service approach reduces system cost while maintaining testing reliability.
Solution Approach 2:
The memory module's data module is designed to serve dual purposes: it functions as a standard data buffer during normal memory operations and simultaneously serves as a test controller and data path during self-testing operations. This multi-functionality eliminates the need for separate dedicated test hardware, reducing overall system complexity and cost while maintaining comprehensive testing capability.
2Reliability
If MBIST is implemented in DRAM chips, then testing capability is improved, but development time and cost increase
Solution Approach 1:
The self-test logic is merged with the existing memory chip structure and integrated into the same fabrication process. The test functionality shares physical and logical resources with the memory array, including using the same data paths, address lines, and control signals. This integration approach eliminates separate development and manufacturing processes, reducing development time and cost while maintaining comprehensive testing capability.
Solution Approach 2:
The memory module performs self-testing at multiple predetermined stages: during manufacturing testing, at system boot-up, and periodically during operation. By performing tests preliminarily during manufacturing, defects are identified early, reducing the need for costly post-manufacturing testing and rework. The embedded MBIST logic is pre-configured and ready to operate without additional development intervention.
3Reliability
If comprehensive memory testing is performed during manufacturing, then memory reliability is improved, but test time and system performance decrease
Solution Approach 1:
The memory system implements periodic self-testing at strategically chosen moments: during manufacturing, at system boot-up, and at intervals during normal operation. This periodic approach ensures memory reliability without requiring continuous testing that would waste time. The tests are performed in brief intervals when the system is idle or transitioning, minimizing impact on overall system performance and throughput.
Solution Approach 2:
During self-testing operations, the memory module maintains its normal functionality where possible. The data module continues to buffer data between the memory array and system bus, and the memory controller can service other memory requests. This continuity ensures that testing does not completely halt system operation, reducing time loss while maintaining memory reliability through comprehensive testing.
4Adaptability or versatility
If ETT DRAM chips are used instead of fully tested chips, then availability is improved, but testing responsibility shifts to module manufacturers
Solution Approach 1:
The memory module incorporates built-in self-test logic that enables the module to perform its own comprehensive testing without requiring external test equipment or complex module-level test processes. This self-service capability allows module manufacturers to use ETT DRAM chips while maintaining full testing responsibility, as the MBIST logic automatically performs necessary validation during manufacturing and operation, simplifying the module test process despite increased chip availability options.
Data Source
AI summary
A memory module comprises memory devices, a data module and a control module. The memory module is operable in a first mode in which at least some of the memory devices are accessed by a system memory controller in a computer system for memory read and/or write operations at a memory access speed, the control module is configured to register address and control signals associated with the memory read and/or write operations, and the data module is configured to propagate data signals between the at least some of the memory devices and the memory controller. The memory module is further operable in a second mode in which the memory devices are not accessed by the system memory controller for memory read or write operations, and the data module is configured to communicate data signals with at least some of the memory devices at the memory access speed.