Semiconductor Memory Module Signal Line Short Circuit Testing
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Solution Overview
Problem
Conventional boundary scanning techniques for semiconductor memory devices require dedicated test pins and complex algorithms, making it difficult to individually test signal line short circuits and locate connection problems, especially when multiple address signals are shared via a single signal line.
Innovation Solution
A semiconductor memory module design that allows individual signal line short circuit testing on each device without additional test pins or algorithms, using a shared signal line set with more test target pins than monitor pins, and employing input and output switching units to connect test signals to monitor pins during a test mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional boundary scanning technique is used for testing semiconductor memory devices, then test coverage can be achieved, but dedicated test pins and complex algorithms are required, increasing device complexity
Solution Approach 1:
The patent applies universality by enabling ordinary signal lines to serve dual purposes: normal data transmission during operation and test signal transmission during testing. The test controller utilizes existing address bus, data bus, and control signal lines to apply test patterns and capture results, eliminating the need for dedicated test pins. This multi-functional use of signal lines reduces device complexity while maintaining test coverage.
Solution Approach 2:
The semiconductor memory device performs self-testing through the test controller that is integrated within the device itself. The test controller generates test patterns, applies them through existing signal lines, captures output data, and determines pass/fail status without requiring external specialized testing equipment or algorithms. This self-service capability simplifies the overall testing system while maintaining comprehensive test coverage.
2Adaptability or versatility
If multiple address signals are shared via a single signal line to reduce pin count, then device integration increases, but individual signal line short circuit testing becomes difficult
Solution Approach 1:
The patent applies segmentation by dividing the shared signal line into multiple independently controllable segments through the test controller. The test controller can selectively activate specific address lines or data lines by controlling the semiconductor memory device's internal multiplexers and registers. This segmentation enables individual testing of each signal line segment even when they share physical conductors during normal operation, allowing precise short circuit detection without sacrificing signal line sharing capabilities.
3Measurement precision
If dedicated test pins are added to enable individual device testing, then testing precision improves, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent eliminates the need for dedicated test pins by making existing signal lines universal. The same address bus, data bus, and control signal lines used during normal operation are utilized during testing by controlling the semiconductor memory device to operate in test mode. This approach achieves precise individual device testing without adding any physical pins, thereby reducing manufacturing cost and simplifying the manufacturing process.
4Reliability
If conventional testing methods are used for densely packed semiconductor memory devices, then connection checking is required, but checking connections between devices and circuit board becomes difficult
Solution Approach 1:
The patent enables the semiconductor memory device to perform self-connection-checking through its integrated test controller. The test controller applies test patterns through the device's signal lines and captures the output to determine if connections to the circuit board are intact. This self-service capability allows easy connection reliability verification for densely packed devices without requiring complex external testing equipment or difficult manual inspection methods.
Data Source
AI summary
A semiconductor memory module and a semiconductor memory device are disclosed. In one embodiment, the invention provides a semiconductor memory module comprising a circuit board, a plurality of semiconductor memory devices adapted to operate during a test mode and a normal operation mode and mounted on the circuit board, a first signal line set comprising a plurality of first signal lines connected to the plurality of semiconductor memory devices, and a plurality of second signal line sets. Each semiconductor memory device comprises first terminals adapted to receive first signals from the first signal lines, second terminals connected to a corresponding one of the second signal line sets, a third terminal adapted to receive an enable signal during the test mode, and a signal transmitting unit adapted to output second signals to the second terminals in response to the enable signal.