Memory Module PCB Layout With Solder Joint Array for Higher Density
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Solution Overview
Problem
Conventional dual-inline memory modules face challenges in achieving high-density small space requirements due to the large area combination of gold fingers and insertion slots, which limits the number of DDR memory chips that can be mounted in a given space.
Innovation Solution
The memory module utilizes a solder joint array on a module PCB to establish communication connections without gold fingers or insertion slots, allowing for a smaller connection region and enabling more memory chips to be mounted in a given area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold finger and insertion slot combination is used, then communication connection is established, but area occupied is large
Solution Approach 1:
The patent extracts and removes the gold finger component from the memory module, replacing it with a solder joint array directly on the PCB. This eliminates the need for insertion slots as well, thereby reducing the connection region area while maintaining communication connection functionality through direct soldering of the solder joints to the target circuit board.
Solution Approach 2:
The patent merges the functions of the gold finger and insertion slot into a single integrated solder joint array structure. The solder joint array serves both as the connection interface and the mounting structure, combining multiple functions into one compact element that reduces overall area occupation.
2Quantity of substance
If more memory chips are mounted, then storage capacity increases, but space requirements increase
Solution Approach 1:
The patent utilizes both surfaces of the module PCB for mounting memory chips, transitioning from single-sided to double-sided mounting. This dimensional change allows memory chips to be arranged on both the front and back surfaces of the PCB, effectively doubling the available mounting area and increasing the number of chips that can be accommodated within the same footprint.
Solution Approach 2:
The patent applies different mounting configurations to different regions of the PCB, with memory chips mounted on both surfaces and the solder joint array positioned in optimized locations. This local optimization allows for high-density chip placement while maintaining proper signal routing and connection areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of the connection region, facilitating higher density and flexibility in memory chip placement, while also simplifying assembly and maintenance processes.
Implementation Method 1
The first connection region includes a first solder joint array. The first solder joint array is configured to implement a connection between the first module PCB and a target circuit board
Data Source
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AI summary
Embodiments of this application disclose a memory module and an electronic device, to meet a requirement of a high-density small space. The memory module provided in embodiments of this application includes a first assembly, and the first assembly includes a first module PCB and at least one first memory chip. The first module PCB includes a first memory region and a first connection region, and the first connection region includes a first solder joint array. The first memory region is configured to mount the at least one first memory chip, and the first solder joint array is configured to implement a connection between the first module PCB and a target circuit board, to establish a communication connection between the first module PCB and the target circuit board.