Synchronous Memory Module Control via Shared Bus Address
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Solution Overview
Problem
In existing memory module control systems, the central processing unit (CPU) cannot transmit commands synchronously to multiple micro control units (MCUs) due to different bus addresses, leading to asynchronous display unit control and increased time for instruction delivery, especially as the number of memory modules increases.
Innovation Solution
The CPU initializes and transmits control signals to MCUs with a preset bus address, allowing all MCUs to have the same bus address, enabling synchronous control of display units and ensuring consistent instruction time across all memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CPU transmits commands to MCUs with different bus addresses, then each memory module can be individually addressed, but the commands cannot be transmitted synchronously and the control time increases
Solution Approach 1:
The patent segments the bus address space into two parts: a common preset bus address (e.g., 0x27) that is shared by all MCUs, and a memory module-specific address that identifies individual modules. This segmentation allows the CPU to transmit commands to all MCUs simultaneously using the common address, while still maintaining the ability to address individual modules through the additional identifier, thereby resolving the contradiction between individual addressing capability and command transmission time
Solution Approach 2:
The patent adds another dimension to the addressing scheme by introducing a memory module-specific address component that works in conjunction with the common preset bus address. This dimensional extension allows the system to maintain both synchronous command transmission (through the common address) and individual module identification (through the additional dimension), eliminating the time loss associated with sequential addressing
2Ease of operation
If the CPU transmits commands to multiple MCUs sequentially, then each MCU can be controlled individually, but the display units cannot work synchronously
Solution Approach 1:
The patent segments the control mechanism into two parts: a common preset bus address that enables synchronous command transmission to all MCUs, and a memory module-specific address that allows individual control when needed. This segmentation resolves the contradiction by allowing the system to operate in synchronous mode (using only the common address) or individual control mode (using both addresses) as required
Solution Approach 2:
The patent implements dynamic addressing flexibility where the CPU can choose to use only the common preset bus address for synchronous control of all display units, or combine the common address with memory module-specific addresses for individual control when necessary. This dynamic adaptability resolves the contradiction between ease of individual control and synchronous operation
3Quantity of substance
If the number of memory modules increases, then the system capacity increases, but the time to instruct all MCUs increases significantly
Solution Approach 1:
The patent segments the addressing into a common preset bus address shared by all MCUs and memory module-specific identifiers. This segmentation allows the CPU to transmit commands to all MCUs simultaneously using the common address, making the instruction delivery time independent of the number of memory modules, thereby resolving the contradiction between system capacity and instruction time
Solution Approach 2:
The common preset bus address serves multiple functions: it enables synchronous command transmission to all MCUs, it provides a universal addressing mechanism that works regardless of the number of memory modules, and it maintains compatibility with individual module identification when needed. This multi-functionality resolves the contradiction by making the addressing mechanism scalable without increasing instruction delivery time
Data Source
AI summary
Embodiments of the present invention relate to a control system and a control method for controlling memory modules. In the embodiments, the control system includes a central processing unit (CPU) and a plurality of memory modules, each of which includes a display unit and a micro control unit (MCU) configured to control the display unit. The CPU and the MCUs are connected through a bus, and the CPU instructs, according to a preset bus address, the MCUs to synchronously control the respective display units.