Memory Module Tag Error Testing via Majority Voting
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Solution Overview
Problem
Existing computing systems face challenges in efficiently integrating nonvolatile memory with volatile RAM, particularly in maintaining data integrity and low power consumption while ensuring compatibility, and in effectively testing tag errors in cache operations.
Innovation Solution
A computing system that includes a nonvolatile memory module with cache DRAMs, where a processor generates match/unmatch bits by comparing tags and determines cache hits/misses through majority voting, and a memory module with a registered connective device that controls cache DRAMs and outputs data based on cache hit/miss information, allowing for error correction and improved cache performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nonvolatile memory is integrated with volatile RAM to provide improved data integrity and low-power characteristics, then data integrity and power efficiency are improved, but compatibility with conventional volatile RAM and system integration complexity may deteriorate
Solution Approach 1:
The memory system is segmented into distinct volatile RAM and nonvolatile memory components, each with specialized functions. The volatile RAM handles high-speed caching while the nonvolatile memory provides persistent storage, allowing each component to be optimized independently while maintaining overall system compatibility and reducing integration complexity through functional separation.
Solution Approach 2:
The memory module is designed to provide multiple functions through a unified interface that supports both volatile and nonvolatile memory operations. The system can operate in different modes (volatile-only, nonvolatile-only, or hybrid) and maintains compatibility with conventional RAM interfaces while adding persistent storage capabilities, making the solution universally applicable across different system configurations.
2Use of energy by moving object
If nonvolatile memory is used as working memory to reduce power consumption, then power efficiency is improved, but access speed and performance may deteriorate
Solution Approach 1:
The memory hierarchy is segmented into fast volatile cache memory for frequently accessed data and slower nonvolatile memory for persistent storage. This segmentation allows the system to maintain high access speeds for active data while using power-efficient nonvolatile storage for less frequently accessed information, optimizing both speed and power consumption.
Solution Approach 2:
The system employs periodic data transfer between volatile and nonvolatile memory based on usage patterns. Frequently accessed data remains in volatile memory for fast access, while idle data is periodically moved to nonvolatile memory to reduce power consumption. This periodic action allows the system to dynamically balance between speed and power efficiency based on actual workload requirements.
Data Source
AI summary
A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.