Memory Module Test Pattern Storage for DRAM Defect Detection
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Solution Overview
Problem
The increasing complexity and defect rate of DRAM manufacturing due to nano-scale technology make existing test operations inefficient, leading to a need for a more effective method to test and identify defects in semiconductor memory devices.
Innovation Solution
A memory module with a test pattern memory that stores and transfers test pattern information to a host device, allowing for the generation of customized test patterns based on the device's characteristics, enabling targeted testing and reducing unnecessary test procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If nano-scale manufacturing technology is used to increase integration and capacity, then manufacturing precision and device capability are improved, but defect rate and test complexity increase
Solution Approach 1:
The patent segments the test operation into multiple phases: initial comprehensive testing during manufacturing, and subsequent targeted testing during supply chain operations. The test pattern memory stores segmented test patterns that can be selectively applied based on the operational context, reducing overall test complexity while maintaining precision.
Solution Approach 2:
The patent changes test parameters dynamically by storing multiple test pattern parameters in the test pattern memory that can be selected based on operational conditions. This allows the test system to adapt parameter sets according to the specific testing needs, reducing complexity for routine tests while maintaining comprehensive coverage when needed.
2Reliability
If comprehensive test operations are performed during manufacturing, then manufacturing reliability is improved, but test time and production efficiency deteriorate
Solution Approach 1:
The patent implements preliminary comprehensive testing during the manufacturing phase when defects are most easily detected and corrected. The test pattern memory stores pre-configured test patterns that enable thorough initial testing. After manufacturing completion, the system switches to more efficient targeted testing approaches, thus maintaining reliability while improving overall production efficiency.
Solution Approach 2:
The patent introduces dynamic test operation modes that can switch between comprehensive testing (during manufacturing) and streamlined testing (during supply chain operations). The test pattern memory enables dynamic selection of appropriate test patterns based on the operational phase, optimizing the balance between reliability and productivity at different stages.
3Ease of operation
If standardized test patterns are used for all DRAM devices, then ease of operation is improved, but measurement precision and defect detection capability deteriorate
Solution Approach 1:
The test pattern memory serves multiple functions: storing standardized test patterns for ease of operation, storing customized test patterns for enhanced defect detection, and selectively providing appropriate patterns based on operational context. This multi-functionality resolves the contradiction by enabling both standardized and customized testing approaches through a single unified system.
Solution Approach 2:
The patent performs preliminary analysis of device characteristics and stores customized test pattern parameters in the test pattern memory before actual testing. This preliminary customization enables precise defect detection while maintaining operational ease, as the system automatically selects pre-configured patterns rather than requiring manual customization for each device.
Data Source
AI summary
A memory module includes at least one semiconductor memory device, and a test pattern memory that stores first test pattern information for testing the at least one semiconductor memory device, and the first test pattern information stored in the test pattern memory is transferred to a host in a test operation. Through the memory module having the above-described function, a memory test is possible in consideration of a unique weak characteristic of the memory module.