Nonvolatile Memory Module Internal Operation Time Management

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Solution Overview

Problem

Existing computing systems face challenges in efficiently managing internal operations of nonvolatile memory modules, as they often require direct communication with hosts for timing approval, leading to inefficiencies and potential interruptions during operations like refresh and data transmission.

Innovation Solution

A method where a nonvolatile memory module or storage device requests and receives internal operation time from a host through dedicated messages or signals, allowing it to perform operations like refresh, calibration, and data transmission autonomously within approved time frames, reducing host intervention and improving operational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the nonvolatile memory module performs internal operations autonomously without host intervention, then operational efficiency and productivity are improved, but the host loses control over timing and scheduling of these operations

Engineering Contradiction:
Improveoperational efficiencyVSAvoidhost control
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The host controller pre-approves internal operation time periods in advance before the memory module executes its internal operations autonomously. This preliminary timing approval mechanism allows the module to operate independently during approved time windows while maintaining host oversight, thus improving productivity without completely losing host control.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If the memory module requests internal operation time from the host, then the host maintains control and scheduling authority, but this communication overhead reduces operational speed and productivity

Engineering Contradiction:
Improvehost controlVSAvoidoperational speed
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The host controller provides timing approval in advance before the memory module needs to perform internal operations. This preliminary action eliminates the need for real-time communication during operation execution, maintaining host control while avoiding communication overhead that would reduce operational speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system establishes periodic timing cycles where the memory module autonomously performs internal operations during pre-approved time windows. This periodic autonomous operation reduces frequent communication between host and module, improving operational speed while the host maintains periodic timing control.

Inventive Principle:
Principle #19Periodic action

3Reliability

If the memory module performs refresh operations autonomously, then operational continuity is maintained without host interruptions, but the complexity of timing management increases

Engineering Contradiction:
Improveoperational continuityVSAvoidtiming management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The host controller pre-defines and communicates timing parameters for refresh operations in advance. The memory module then autonomously executes these refresh operations during the pre-approved time periods without requiring real-time host intervention, ensuring operational continuity while simplifying the actual execution complexity through prior timing setup.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11481149B2Memory module and memory system relating thereto
Publication Date: 2022.10.25 SAMSUNG ELECTRONICS CO LTD
  • US11481149B2 patent drawing
  • US11481149B2 patent drawing
  • US11481149B2 patent drawing

AI summary

A memory module including at least one memory and a memory control circuit to control the at least one memory and to generate an internal operation request including an information regarding internal operation time when the memory module need the internal operation time. The memory control circuit is to transfer the internal operation request to an external device, to receive a first command from the external device in response to the internal operation request and including an information of whether the internal operation time is approved, and to perform the internal operation during the internal operation time based on the first command.