Memory Module With Unlimited Read Retries For DRAM Speed Compatibility

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Solution Overview

Problem

The integration of storage class memory (SCM) with dynamic random access memory (DRAM) is hindered by differences in operating characteristics between volatile and nonvolatile memory devices, leading to issues with read and write speed compatibility.

Innovation Solution

A memory system comprising a nonvolatile memory module and controllers that allow for unlimited retransmissions of read and write requests during operations, ensuring compatibility with DRAM speeds by using a volatile memory device and a nonvolatile memory device, with a controller managing data transfer and error handling through SMBus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If storage class memory is implemented using nonvolatile memory for compatibility with existing main memory, then storage capacity is improved, but read and write speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidread and write speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The memory system is divided into two independent memory devices: a volatile memory device for high-speed operations and a nonvolatile memory device for large storage capacity. Each device is accessed through separate controllers, allowing the system to leverage the speed advantage of volatile memory for frequently accessed data while utilizing the capacity advantage of nonvolatile memory for bulk storage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A controller acts as an intermediary between the host system and the memory devices, managing data transfer between volatile and nonvolatile memory. The controller coordinates read and write operations to ensure seamless data access while accommodating the different operating characteristics of the two memory types.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If read requests are repeated without limitation to accommodate slower nonvolatile memory speed, then read reliability is improved, but system complexity increases

Engineering Contradiction:
Improveread reliabilityVSAvoidcontroller complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The controller dynamically adjusts read operation parameters based on the specific memory device being accessed. For nonvolatile memory, the controller implements unlimited read retries to ensure data retrieval, while for volatile memory, standard read timing is used. This dynamic adaptation allows the system to maintain high read reliability without implementing complex retry mechanisms across all memory operations.

Inventive Principle:
Principle #15Dynamics

3Reliability

If write operations are performed with error signals activated during nonvolatile memory writing, then write reliability is improved, but operation time increases

Engineering Contradiction:
Improvewrite reliabilityVSAvoidwrite operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller activates write error signals in advance during nonvolatile memory write operations to prepare for potential write failures. This preliminary error detection mechanism allows the system to identify and correct write issues before they affect data integrity, improving write reliability without significantly increasing the overall write operation time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11210208B2Memory system including memory module, memory module, and operating method of memory module
Publication Date: 2021.12.28 SAMSUNG ELECTRONICS CO LTD
  • US11210208B2 patent drawing
  • US11210208B2 patent drawing
  • US11210208B2 patent drawing

AI summary

A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.