Memory Module Wiring Pattern for Signal Reflection Reduction
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Solution Overview
Problem
In Fully Buffered memory modules, signal reflections from memory chips mounted on the back surface of the memory buffer distort waveforms, making high-speed data transmission difficult due to longer wiring lengths and increased signal load, and existing solutions like terminating resistors or complex wiring adjustments are impractical.
Innovation Solution
The memory module design positions a first branch point at the control chip side, ensuring short wiring lengths for memory chips, and uses a common wiring pattern to connect the control chip to memory chips, with specific branch points positioned between the control chip and memory chip mounting positions to minimize signal reflections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are mounted on the back surface of the memory buffer to maximize mounting capacity, then the number of memory chips increases, but the wiring length increases and signal reflection distorts waveforms
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by mounting memory chips on both the front and back surfaces of the memory buffer. This allows memory chips to be arranged in multiple layers rather than just a single plane, effectively increasing storage capacity while managing wiring length through strategic placement on opposite surfaces.
Solution Approach 2:
The patent employs asymmetric wiring patterns where branch points are positioned at different locations depending on which surface the memory chip is mounted on. Memory chips on the front surface have branch points positioned differently than those on the back surface, optimizing signal paths for each location and reducing overall wiring length despite the three-dimensional arrangement.
2Quantity of substance
If memory chips are mounted on the back surface of the memory buffer, then mounting density increases, but signal reflection from chip terminals distorts output waveforms
Solution Approach 1:
The patent applies different wiring patterns and branch point positions tailored to specific locations. Memory chips mounted on the front surface receive optimized wiring configurations different from those on the back surface, with each location's signal path specifically designed to minimize reflection and maintain waveform integrity.
Solution Approach 2:
The patent modifies wiring parameters such as branch point position, wiring route, and connection topology based on the specific location of memory chips. By adjusting these parameters for different mounting positions, the system maintains signal quality while accommodating high-density three-dimensional chip arrangements.
3Device complexity
If conventional wiring patterns are used for memory chips on the back surface, then wiring complexity increases, but high-speed data transmission becomes difficult due to waveform distortion
Solution Approach 1:
The patent divides the wiring system into separate, optimized segments for front-surface and back-surface memory chips. Each segment has its own branch point positioning and wiring configuration, allowing independent optimization of signal paths. This segmentation prevents complex interactions between wires and maintains waveform integrity for high-speed transmission.
Solution Approach 2:
Instead of extending wires from the memory buffer to reach back-surface chips (which increases length and complexity), the patent inverts the approach by positioning branch points closer to the memory buffer on the front surface and routing wires efficiently to back-surface chips. This inverted wiring topology reduces overall wire length and simplifies the wiring pattern while maintaining signal quality.
Data Source
AI summary
A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.