3D Memory Mold Structure With Dummy Blocks for Reliable Signal Routing

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Solution Overview

Problem

The integration density of two-dimensional semiconductor devices is limited due to the high cost of equipment required for miniaturization, and there is a need for more efficient three-dimensional semiconductor memory devices with improved reliability.

Innovation Solution

The semiconductor memory device incorporates a mold structure with stacked gate electrodes, channel structures, and through structures that include memory cell blocks and dummy blocks with extension regions, allowing for increased integration density and improved signal transmission through upper and lower metal lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If two-dimensional semiconductor devices are miniaturized to increase integration density, then integration density is improved, but equipment cost increases significantly

Engineering Contradiction:
Improveintegration densityVSAvoidequipment cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar device architecture to three-dimensional stacked architecture by vertically stacking multiple mold structures, each containing memory cell blocks and dummy blocks. This vertical stacking enables increased integration density without requiring further miniaturization of individual two-dimensional device features, thereby avoiding the need for extremely high-priced equipment while achieving higher capacity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If three-dimensional semiconductor memory devices are designed to increase integration density, then integration density is improved, but device reliability may deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoiddevice reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the three-dimensional structure into multiple independent mold structures stacked vertically, with each mold structure containing memory cell blocks and dummy blocks. This segmentation allows each stack to function independently, improving reliability by isolating potential failures to individual stacks rather than affecting the entire device. The segmentation also facilitates modular manufacturing and testing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements different block types (memory cell blocks and dummy blocks) within each mold structure, where dummy blocks serve specific functions such as providing structural support, enabling selective fabrication processes, and improving signal transmission characteristics. This local differentiation of block qualities enhances overall device reliability while maintaining high integration density

Inventive Principle:
Principle #3Local quality

3Area of stationary object

If mold structures are stacked vertically to increase integration density, then space utilization is improved, but signal transmission complexity increases

Engineering Contradiction:
Improvespace utilizationVSAvoidsignal transmission complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent introduces extension regions and extension through structures as intermediary elements between the memory cell blocks and the external environment. These extension regions provide dedicated pathways for signal transmission, acting as mediators that simplify the complex routing required in three-dimensional stacked architectures. The extension through structures establish clear vertical connections between stacked mold structures, reducing signal transmission complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11950425B2Semiconductor memory device with mold structure
Publication Date: 2024.04.02 SAMSUNG ELECTRONICS CO LTD
  • US11950425B2 patent drawing
  • US11950425B2 patent drawing
  • US11950425B2 patent drawing

AI summary

A mold structure includes gate electrodes stacked on a first substrate, a channel structure penetrating a first region of the mold structure to cross the gate electrodes, a first through structure penetrating a second region of the mold structure, and a second through structure penetrating a third region of the mold structure. The mold structure includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell and dummy blocks includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.