Memory Device Single Multiplexer Bit Line Selection
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Solution Overview
Problem
Current memory devices, such as RRAM, face challenges in efficiently managing the switching between high and low resistance states for data storage due to complex circuitry and increased costs associated with multiple multiplexers required for selecting bit lines.
Innovation Solution
A memory device design that incorporates a single multiplexer for selecting bit lines within an I/O memory block, with a source line configuration having a main portion and branch portions, allowing for reduced circuit area and manufacturing costs by eliminating the need for additional multiplexers, and utilizing a switch group to control writing and resetting states of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple multiplexers are used for selecting bit lines in memory devices, then data storage capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the functions of multiple multiplexers into a single multiplexer by utilizing the source line structure (main portion and branch portions) to provide selective connectivity. This consolidation reduces device complexity while maintaining the ability to select and access multiple bit lines for data storage operations.
Solution Approach 2:
The source line is designed with multi-functionality, serving both as a main conductor and as a selector mechanism through its branch portions. This universal structure eliminates the need for dedicated multiplexer circuits, reducing overall device complexity while preserving data storage capabilities.
2Ease of operation
If multiple multiplexers are used for selecting bit lines, then memory cell accessibility is improved, but manufacturing cost increases
Solution Approach 1:
By combining multiple multiplexer functions into a single multiplexer with the source line structure, the patent reduces the number of components that need to be manufactured and assembled, thereby lowering manufacturing costs while maintaining full accessibility to all memory cells through the branch portions.
3Adaptability or versatility
If complex circuitry with multiple multiplexers is used, then bit line selection capability is improved, but circuit area increases
Solution Approach 1:
The patent merges multiple multiplexer circuits into a single multiplexer implementation, significantly reducing the circuit area occupied by selection logic. The source line structure provides the necessary routing functionality without requiring additional multiplexer circuitry, thus maintaining bit line selection capability while minimizing area usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the memory device architecture, reduces circuit area, and lowers manufacturing costs while maintaining efficient data storage capabilities by effectively switching between resistance states using a single multiplexer and optimized source line configuration.
Implementation Method 1
The above switching mechanism is related to oxygen vacancy migration
Data Source
AI summary
A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.