Memory Device Multiplexer Isolation Logic for Leakage Reduction
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Solution Overview
Problem
As memory devices shrink, leakage current increases, leading to high power consumption, and existing precharging techniques are hindered by capacitance in multiplexer logic, affecting the speed of data state detection in memory cells.
Innovation Solution
Incorporating isolation logic between the sense amp precharge node and multiplexer output to isolate capacitance, and using self-timing path logic to accurately determine the output enable signal timing, thereby improving the speed and reducing power consumption of memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory device size is reduced, then device area is improved, but power consumption increases due to increased leakage current
Solution Approach 1:
The patent segments the bit lines into multiple groups, each group associated with a separate precharge transistor. This allows selective precharging of only the necessary bit line groups rather than all bit lines, reducing the total leakage current that must be compensated and thereby reducing power consumption in scaled-down memory devices.
Solution Approach 2:
The patent applies partial precharging by activating only a subset of precharge transistors based on the address being accessed. Instead of precharging all bit lines (excessive action), only the bit lines that may be accessed are precharged (partial action), reducing the overall power consumption while still preventing leakage current issues in the scaled device.
2Use of energy by moving object
If selective precharging of bit lines is implemented, then power consumption is reduced, but the capacitance of multiplexer logic affects the speed of data state detection
Solution Approach 1:
The patent extracts the capacitance problem by separating the multiplexer logic from the critical sensing path. The multiplexer output drives a precharge node that is isolated from the sense amplifier input capacitance during the sensing operation, allowing fast detection without being burdened by the multiplexer's output capacitance.
Solution Approach 2:
The patent performs preliminary precharging of the bit lines and precharge node before the actual sensing operation. This preliminary action prepares the circuit in advance so that when sensing begins, the capacitive effects have already been charged, and the sense amplifier can detect voltage changes rapidly without being slowed by charging large capacitances during the critical detection window.
3Duration of action of stationary object
If precharge transistor is turned on during clock high period, then bit line is precharged, but address decoding must be completed quickly enough to activate the correct pass transistor before precharging
Solution Approach 1:
The patent performs preliminary address decoding during the clock high period, before the precharge operation begins. The decoded address information is used to pre-enable the correct pass transistor and select the appropriate bit line group. This preliminary decoding ensures that when the precharge transistor turns on, the correct circuit path is already established, eliminating timing conflicts.
Solution Approach 2:
The patent segments the address decoding into multiple stages: preliminary decoding that occurs during the clock high period to select bit line groups, and final decoding that occurs during the clock low period to select specific bit lines. This segmentation allows the precharge operation to proceed without waiting for complete address decoding, reducing the time loss.
Data Source
AI summary
A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected to its inputs, and is arranged to connect one of those inputs to its output dependent on a multiplexer control signal. Decoder logic is responsive to an address to produce the multiplexer control signal and to select one of the word lines, as a result of which a particular memory cell in the memory array identified by the address has its associated bit line connected to the output of a multiplexer logic. Sense amp logic is coupled to the output of the multiplexer logic and has a precharge node used during a sensing operation to detect a stored data state of the particular memory cell. Control logic initiates the sensing operation and causes the precharge node of the sense amp and at least the bit line associated with the particular memory cell to be precharged in a precharge operation prior to the sensing operation. Further, isolation logic is provided between the output of the multiplexer logic and the precharge node of the sense amp logic to isolate the precharge node from the capacitance of the output of the multiplexer logic during the sensing operation.