Semiconductor Memory Device Multiplexer Layout
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Solution Overview
Problem
Current semiconductor memory devices face challenges in size reduction due to the inefficient placement and connectivity of multiplexers, which leads to increased size and dead spaces in the memory cell array layout.
Innovation Solution
The semiconductor memory device employs a configuration with multiple multiplexers strategically placed in different regions, including a first multiplexer extending in the second direction and a second multiplexer extending in the first direction, connected by specific wirings to optimize the layout and reduce the overall size by effectively utilizing the available space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiplexers are placed in conventional positions within the memory cell array, then connectivity is maintained, but device size increases and dead spaces are created
Solution Approach 1:
The patent moves multiplexers from the traditional planar placement within the memory cell array to a three-dimensional configuration where multiplexers are positioned at the periphery and connected via vertical connection wirings. This dimensional transition eliminates dead spaces within the memory cell array while maintaining all necessary connectivity functions.
Solution Approach 2:
The patent extracts multiplexers from the interior of the memory cell array and relocates them to peripheral regions. This extraction removes the multiplexers from the active memory area, eliminating the dead spaces they previously occupied while preserving their switching and multiplexing functions through dedicated connection wirings.
2Area of stationary object
If multiplexers are relocated to reduce dead spaces, then area utilization improves, but wiring complexity increases
Solution Approach 1:
The patent merges the functions of multiple connection wirings into shared vertical pathways that connect multiplexers to memory cell arrays. By consolidating connection routes and using common vertical interconnect structures, the wiring complexity is reduced despite the relocated multiplexer positions.
Solution Approach 2:
The patent introduces vertical connection wirings that extend in the third dimension (depth) to connect peripheral multiplexers to memory cell arrays. This three-dimensional wiring approach consolidates connection pathways and reduces the overall wiring complexity compared to planar routing methods.
3Area of stationary object
If connection wirings extend vertically to connect multiplexers, then space efficiency improves, but voltage loss increases
Solution Approach 1:
The patent applies different material properties or structural characteristics to specific regions of the vertical connection wirings. By optimizing the local quality of wiring materials, cross-section areas, or insulation properties in critical voltage transmission zones, the patent reduces voltage loss while maintaining the space-efficient vertical connection architecture.
Data Source
AI summary
A semiconductor memory device includes first wirings above a substrate and extending in a first direction, second wirings above the first wirings and extending in a second direction crossing the first direction, third wirings above the second wirings and extending in the first direction, memory cells between the first and second wirings and between the second and third wirings, a first multiplexer that extends in the second direction, is connected to the first wirings, and is provided in a first region which overlaps with the first, second, and third wirings in a third direction that crosses the first and second directions, and a second multiplexer that extends in the first direction, is connected to the second wirings, and is provided in a second region which overlaps with the first, second, and third wirings in the third direction.