Memory Multiplication via Selective Word Line Activation
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Solution Overview
Problem
Existing memory systems for electronic systems lack efficient mechanisms for performing multiplication operations directly within the memory, requiring separate processor involvement and incurring additional time and energy costs, while also facing weight value coherency issues and inefficient power management.
Innovation Solution
A memory system with a row decoder that selectively activates word lines based on operand bit values to perform multiplication mode read operations, allowing direct multiplication of input data bits by stored weight values within the memory array, utilizing nonvolatile bitcells like MRAM or ReRAM for efficient and simultaneous data read and multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multiplication operations are performed outside the memory system using separate processors, then computational flexibility is maintained, but time and energy consumption increase
Solution Approach 1:
The patent combines multiplication functionality directly into the memory system by integrating a row decoder that selectively activates word lines based on operand bit values. This merging of storage and computation functions eliminates the need for separate processors to perform multiplication operations, thereby reducing energy consumption while accepting increased device complexity within the memory architecture.
Solution Approach 2:
The memory system is designed to perform multiple functions: it can operate in standard read mode for data retrieval and in multiplication mode for computational operations. The row decoder and sense amplifiers are configured to handle both data access and weighted multiplication, making the memory system universal and reducing reliance on external computational units.
2Speed
If weight values are stored in volatile memory, then fast access is achieved, but weight value coherency issues arise during power cycles
Solution Approach 1:
The system performs preliminary actions by pre-computing and storing multiplication results in the memory array during initialization or training phases. These pre-computed weight values are persisted in nonvolatile memory, ensuring coherency across power cycles. When needed, the system retrieves these pre-stored values and performs multiplication by selectively activating word lines, thus maintaining both speed and reliability.
3Adaptability or versatility
If standard read operations are used for data retrieval, then operational simplicity is maintained, but multiplication functionality is not available
Solution Approach 1:
The row decoder is designed to be dynamic, switching between standard read mode and multiplication mode based on operational requirements. In standard read mode, the decoder functions conventionally to retrieve data. In multiplication mode, it selectively activates word lines based on operand bit values to perform weighted multiplication. This dynamic reconfiguration enables the memory system to adapt to different operational modes while managing device complexity through unified hardware design.
Data Source
AI summary
A memory includes a row decoder that receives an address of a row to be read and an operand. The memory includes a memory array of bitcells that can be configured to store N-bit weight values in which N is an integer greater than one. The row decoder is configured to, for a multiplication mode read operation at the selected word line, selectively activate the selected word line based on a bit value of the received operand to selectively read an N-bit weight value based on a bit value of the operand. Such an operation may in some embodiments, perform a multiplication operation of the bit value of the operand and the N-bit weight value.