Memory Circuit Multi-Row Activation for In-Memory Calculation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory circuits are limited in their ability to perform calculation operations by simultaneously activating multiple rows for logic and arithmetic operations, and there is a need for improved control mechanisms to enable seamless cooperation between memory circuits and microprocessors for both conventional and intelligent memory operations.
Innovation Solution
A memory circuit with an internal control circuit that reads mode selection signals to perform read/write operations on single or multiple rows, including the capability to execute calculation operations by activating multiple rows based on instruction signals, using a row selection circuit to generate a row selection vector from the instruction signal, and a system that includes a microprocessor coupled to the memory circuit via data, address, and mode selection buses to control these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory circuit simultaneously activates multiple rows to perform calculation operations, then the calculation capability and productivity are improved, but the control complexity and device complexity increase
Solution Approach 1:
The memory circuit is designed to perform multiple functions: conventional single-row read/write operations and simultaneous multi-row calculation operations. The control circuit interprets address signals differently based on the operation type, enabling the same hardware to serve both traditional memory access and in-memory computation needs without requiring separate dedicated circuits for each function.
Solution Approach 2:
The control circuit dynamically adjusts its behavior based on the operation type. When a calculation operation is detected (through specific address signal patterns), the control circuit activates multiple rows simultaneously; for conventional operations, it activates only the addressed row. This dynamic adaptation allows the system to optimize performance for different operation types without permanent structural changes.
2Speed
If the memory circuit performs calculation operations by simultaneously activating multiple rows, then the processing speed is improved, but the power consumption increases
Solution Approach 1:
Instead of activating the entire memory array for calculation operations, the system selectively activates only the specific rows that contain the required data for the calculation. This localized activation approach maintains high processing speed by parallelizing operations across necessary rows while minimizing power consumption by leaving the rest of the memory array in a low-power state.
3Adaptability or versatility
If the memory circuit is designed to support both conventional and intelligent memory operations, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The memory circuit incorporates a unified control mechanism that handles both conventional single-row operations and intelligent multi-row calculation operations through the same hardware interface. The control circuit detects the operation type from the address signal format and automatically configures itself to perform the appropriate function, eliminating the need for separate control circuits for each operation mode.
Solution Approach 2:
Instead of using different control mechanisms for different operation types, the system inverts the approach by using a single control mechanism that adapts its behavior based on the incoming address signals. Conventional operations use standard address formats, while calculation operations use specially formatted addresses that trigger the multi-row activation logic, thereby simplifying the overall control architecture.
Data Source
AI summary
A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.