Memory Namespace Binding for Latency-Aware Process Allocation

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Solution Overview

Problem

Existing computer systems lack awareness of how virtual address ranges are mapped to different memory devices, leading to processes being forced to run slowly due to slow memory access when data is stored in slower physical memory devices, causing significant delays.

Innovation Solution

The system stores metadata on memory device latencies and uses this information to allocate processes to address ranges with appropriate memory latency, automatically transferring applications between memory types based on priority changes or application requests, ensuring faster memory access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in slower physical memory devices, then storage capacity is improved, but process execution speed deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidprocess execution speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The system applies local quality by associating different memory types (fast and slow) with different address ranges, allowing high-priority processes to access fast memory while low-priority processes use slow memory. The MMU translates virtual addresses to physical addresses based on process priority, ensuring each process receives appropriate memory quality without requiring uniform fast memory for all processes.

Inventive Principle:
Principle #3Local quality

2Device complexity

If the system is unaware of virtual address range mappings to memory devices, then system complexity is reduced, but memory access performance deteriorates

Engineering Contradiction:
Improvesystem complexityVSAvoidmemory access delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The system performs preliminary action by pre-establishing associations between virtual address ranges and memory types through metadata storage. The MMU is pre-configured with translation rules that map virtual addresses to appropriate physical memory devices based on process priority. This preliminary setup eliminates the need for real-time complex analysis during memory access, reducing both system complexity and access delay.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If processes are allocated to address ranges without considering memory latency, then allocation simplicity is improved, but process execution efficiency deteriorates

Engineering Contradiction:
Improveallocation simplicityVSAvoidprocess execution efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system applies dynamics by making memory allocation adaptive to process priority changes. The OS monitors process priority and dynamically updates the association between virtual address ranges and memory types. When process priority changes, the MMU automatically adjusts address translations to redirect access between fast and slow memory devices, maintaining execution efficiency without complex manual reallocation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12566714B2Memory system for binding data to a memory namespace
Publication Date: 2026.03.03 MICRON TECHNOLOGY INC
  • US12566714B2 patent drawing
  • US12566714B2 patent drawing
  • US12566714B2 patent drawing

AI summary

A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, an operating system allocates memory from a namespace for use by an application. The namespace is a logical reference to physical memory devices in which physical addresses are defined. The namespace is bound to a memory type. In response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.