Memory Processing with Narrow Data Ports and Address Conversion
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Solution Overview
Problem
Computing devices with narrow data buses in memory chips face challenges in performing in-memory processing due to the inability of memory processors to access the full width of data from host processors, leading to inefficiencies in data transfer and energy consumption.
Innovation Solution
A computing device architecture that includes a first processing device and multiple memory circuits with narrow data ports, where the data bus width is wider than the memory circuit data ports, allowing for address conversion and cache line permutation to enable efficient read/write operations across multiple memory access operations, thereby allowing memory processors to perform data processing tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If memory chips use narrow data ports to reduce pin count and energy consumption, then energy consumption is reduced, but the processor cannot access the full width of host processor data
Solution Approach 1:
The patent divides the data access process into multiple segments by using multiple memory access operations to transfer data across a narrow data port. The host processor's wide data bus is segmented into multiple transactions, each fitting the narrow data port width, allowing full data width access despite the limited port size.
Solution Approach 2:
The patent implements preliminary address conversion to translate host processor addresses into memory circuit addresses before data transfer. This preliminary action enables the system to prepare the correct addressing scheme in advance, allowing the narrow data port to access any location in the host processor's address space without limitation.
2Device complexity
If data bus is sliced into narrow ports per memory chip, then device complexity is reduced, but productivity of data processing is reduced
Solution Approach 1:
The patent maintains continuous useful action by implementing pipelined memory access operations. While one data transfer is in progress, the address conversion for the next transfer is being prepared, and subsequent transfers are queued. This continuous operation minimizes idle time and maintains high productivity despite the narrow data port width.
3Adaptability or versatility
If address conversion is implemented to enable wide data access through narrow ports, then data access capability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal address conversion mechanism that handles multiple memory circuits with different narrow data port widths through a single conversion system. The address conversion circuitry is designed to be configurable and adaptable to various data port widths, making it a multi-functional component that serves all memory circuits regardless of their specific port size.
Data Source
AI summary
A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.