Semiconductor Memory NBTI Prevention via Self-Refresh Node Transition
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Solution Overview
Problem
Semiconductor memory devices face performance degradation due to negative bias temperature instability (NBTI) in p-channel metal-oxide-semiconductor (PMOS) transistors caused by temperature changes and high electric fields during refresh operations.
Innovation Solution
A semiconductor memory device design that includes a command decoder, oscillator, refresh controller, and delay unit to generate self-refresh commands and signals, which prevent NBTI by transitioning internal nodes to ground voltage during refresh periods, using a combination of PMOS and NMOS transistors and inverters to manage electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed in semiconductor memory devices, then data retention is maintained, but negative bias temperature instability (NBTI) occurs in PMOS transistors due to high electric fields and temperature changes
Solution Approach 1:
The patent applies preliminary action by transitioning internal nodes to ground voltage before the refresh operation completes. The delay unit is configured to transition internal nodes during the refresh period, specifically connecting them to ground voltage through NMOS transistors before the PMOS transistors experience damaging high electric fields, thereby preventing NBTI degradation before it occurs
Solution Approach 2:
The patent implements periodic action by using the oscillation signal from the oscillator to periodically control the refresh operations and the associated internal node transitions. The refresh controller generates refresh control signals that periodically activate the delay unit to transition internal nodes during each refresh period, creating a periodic pattern that prevents cumulative NBTI damage while maintaining data retention
2Productivity
If high electric fields are applied to PMOS transistors during refresh operations, then refresh functionality is achieved, but threshold voltage increases and device performance degrades
Solution Approach 1:
The patent uses an intermediary approach by introducing NMOS transistors and the delay unit as intermediary elements between the refresh control signals and the PMOS transistors. These intermediaries actively transition internal nodes to ground voltage during the refresh period, mediating the electric field conditions to prevent direct high-field stress on PMOS transistors while still enabling the refresh operation to complete successfully
Data Source
AI summary
A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.