Semiconductor Memory Negative Voltage Supply Unit

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Solution Overview

Problem

The increasing demand for high-speed reading in semiconductor memory systems requires a negative voltage to be applied to the word line, but existing solutions take too long to establish, leading to increased power consumption in standby mode due to the need for real-time startup during read operations.

Innovation Solution

A semiconductor memory with a negative voltage supply unit that includes a clamping unit and an energy storage capacitor, allowing for quick establishment of a negative voltage on the word line during read operations by using a read operation enable signal and its inverted signal to control voltage clamping, reducing static DC power consumption and enabling real-time startup.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a negative voltage supply unit is designed to establish negative voltage quickly for high-speed reading, then reading speed is improved, but power consumption increases due to real-time startup requirements

Engineering Contradiction:
Improvereading speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The energy storage capacitor is pre-charged to a first voltage level before read operations. When a read operation is initiated, the capacitor is rapidly discharged to establish the negative voltage on the word line, eliminating the need for continuous power supply and reducing standby power consumption while enabling fast read operations

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the negative voltage establishment time is reduced for real-time startup, then productivity is improved, but energy loss increases due to frequent voltage transitions

Engineering Contradiction:
Improvereal-time startup capabilityVSAvoidenergy loss during voltage transitions
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The energy storage capacitor is periodically charged during idle periods and discharged only when read operations are required. This periodic charging strategy allows the system to maintain readiness for fast startup while minimizing the frequency of voltage transitions, thereby reducing energy loss

Inventive Principle:
Principle #19Periodic action

3Reliability

If the clamping unit holds the output terminal at ground voltage when first signal is '0

Engineering Contradiction:
Improvevoltage stabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The clamping unit acts as an intermediary between the energy storage capacitor and the word line. It provides a stable reference potential (ground voltage) when not in use, ensuring reliable voltage levels for memory cells, while simplifying the overall circuit design by eliminating the need for complex voltage regulation mechanisms

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for real-time startup and reduces power consumption by minimizing the time required to establish the negative voltage, meeting high-speed read operation requirements while maintaining low power usage, even as memory capacity increases.

Implementation Method 1

an energy storage capacitor having a first terminal coupled to the output terminal and a second terminal configured to receive a second signal

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The clamping unit is configured to pull a voltage of the output terminal to a voltage of the input terminal when the first signal is '0', and further configured to clamp the output terminal at a clamp voltage when the first signal is '1'

Methodology Applied
Scientific EffectVoltage clamping:

Data Source

PatentUS12165714B2Semiconductor memory
Publication Date: 2024.12.10 CSMC TECH FAB2 CO LTD
  • US12165714B2 patent drawing
  • US12165714B2 patent drawing

AI summary

A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.