Unified Memory Network Routing Logic for I/O and Data Traffic
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Solution Overview
Problem
Current computer networks and systems face challenges in achieving fast response times and scalable memory solutions, particularly in applications like telecommunication and big-data workloads, as they rely on traditional hard drives and lack efficient memory traffic management.
Innovation Solution
A memory network architecture that utilizes high-speed interconnects and memory nodes with co-memory controllers and routing logic to create a unified, scalable, and high-performance memory system that supports both memory and I/O traffic, allowing processors to use the same physical infrastructure for memory access and data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional hard drives are used for data storage, then data capacity can be maintained, but response time becomes slow
Solution Approach 1:
The patent merges memory and I/O operations into a unified memory network infrastructure. Memory nodes serve dual purposes: storing data for fast access and routing I/O traffic. This consolidation eliminates the need for separate storage hardware while achieving memory-speed response times for data access.
Solution Approach 2:
Memory nodes are designed with multi-functionality, acting as both storage units and I/O routing devices. The same physical infrastructure handles both memory traffic and I/O traffic, allowing the system to maintain large data capacity while providing fast response times through direct memory access.
2Device complexity
If dedicated I/O channels are implemented, then I/O traffic can be handled separately, but device complexity and number of channels increase
Solution Approach 1:
The memory network infrastructure is designed to handle multiple types of traffic (memory and I/O) through the same physical channels and pins. Memory nodes are equipped with routing logic that can direct different traffic types through the unified network, reducing device complexity while maintaining full adaptability.
Solution Approach 2:
The system segments traffic handling at the node level rather than requiring separate physical channels. Each memory node contains routing logic that independently directs memory traffic and I/O traffic appropriately, allowing complex routing capabilities without increasing the number of physical channels or pins.
3Device complexity
If memory nodes handle both memory and I/O traffic, then infrastructure density increases, but routing complexity at nodes increases
Solution Approach 1:
Routing complexity is segmented and distributed to individual memory nodes rather than centralized. Each node contains localized routing logic that handles traffic direction independently, enabling high system density without requiring complex centralized routing infrastructure.
Data Source
AI summary
According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.