Non-Volatile Memory Neural Array for Energy-Efficient Image Scanning
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Solution Overview
Problem
The development of high-performance artificial neural networks is hindered by a lack of adequate hardware technology, particularly in terms of energy efficiency and the ability to provide pixel values as inputs for effective multiplication by predetermined weights, and existing CMOS-implemented synapses are too bulky for practical neural networks.
Innovation Solution
A method utilizing a non-volatile memory array with reconfigured lines to enable individual programming, erasing, and reading of memory cells, combined with analog programming, to store and tune synapse weights efficiently, and a vector-by-matrix multiplication array for scanning images using non-volatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then computational parallelism is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent replaces digital computational systems (supercomputers, GPU clusters) with an analog neural network implementation using non-volatile memory cells. The memory cells directly perform analog multiplication of inputs by weights through physical electrical properties, eliminating the need for digital computation cycles and associated energy consumption, thereby achieving both high computational parallelism and improved energy efficiency
Solution Approach 2:
The patent changes the operational parameters from digital discrete values to analog continuous values. By using analog voltages and currents to represent neural signals and weights, the system achieves simultaneous high computational parallelism through physical analog processing and improved energy efficiency by operating in the analog domain rather than requiring energy-intensive digital conversion and processing
2Use of energy by moving object
If CMOS analog circuits are used for artificial neural networks, then energy efficiency is improved, but device area increases due to bulky synapse implementation
Solution Approach 1:
The patent makes non-volatile memory cells multi-functional by configuring them to simultaneously serve as weight storage and as analog multipliers for synaptic computation. This universal use of the same hardware structure for both storage and computation eliminates the need for separate bulky analog circuitry, achieving energy efficiency through analog operation while maintaining compact device area through the inherent compactness of memory cell structures
Solution Approach 2:
The patent merges the functions of weight storage and synaptic computation into a single integrated structure using non-volatile memory cells. By combining what would traditionally be separate components (weight registers and analog multipliers) into one unified memory-based structure, the system achieves both energy efficiency from analog operation and compact area utilization from the integrated design
3Productivity
If a large number of synapses are implemented to enable high connectivity between neurons, then computational parallelism is improved, but device complexity increases
Solution Approach 1:
The patent segments the neural network into discrete layers of neurons and synapses, where each non-volatile memory cell represents a individual synapse with its own configurable weight. This segmentation allows for systematic scaling of computational parallelism by simply adding more memory cells in an organized array structure, managing device complexity through modular organization rather than monolithic design
Solution Approach 2:
The patent implements dynamic configurability of synapse weights through programmable non-volatile memory cells. Each synapse weight can be independently tuned and updated, allowing the network to adapt its connectivity and computational capabilities. This dynamic property enables high computational parallelism to be achieved and adjusted as needed, while complexity is managed through software-controlled configuration rather than fixed hardware design
Data Source
AI summary
A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.