Defect-Tolerant Memory-Based Neural Network Weight Rearrangement
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Solution Overview
Problem
Artificial neural networks (ANNs) based on hardware memory cell arrays face challenges in accuracy due to defective cells, which affect the signal transmission efficiency between neurons.
Innovation Solution
The method involves determining a weight pattern sensitivity (WPS) and a defect pattern for the memory cell array, then rearranging the weight pattern and input data based on these patterns to minimize the impact of defects, thereby improving the network's tolerance to defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If weight patterns are stored directly in memory cell arrays, then hardware implementation is simple, but defective cells reduce neural network accuracy
Solution Approach 1:
The patent performs preliminary characterization of memory cell defects during manufacturing by applying test patterns and measuring signal responses. Defective cells are identified and mapped before the actual neural network operation, allowing the system to compensate for them in advance through weight pattern rearrangement and defect-aware processing, thus maintaining accuracy without requiring complex real-time defect detection mechanisms
Solution Approach 2:
The patent changes the storage parameters of weight patterns by transposing them from row-major to column-major organization in the memory array. This parameter change allows the system to store weight patterns in a different arrangement that avoids defective cells during neural network computation, effectively compensating for cell defects while maintaining the same functional output
2Ease of manufacture
If defective cells are present in memory arrays, then manufacturing yield decreases, but replacing all defective cells increases device complexity
Solution Approach 1:
The patent extracts and removes defective cells from the active neural network computation by identifying them during characterization and excluding them from the weight pattern storage. By taking out defective cells and creating a mapping of their locations, the system can reroute weight patterns around these excluded cells, maintaining functional integrity without requiring physical replacement or complex repair mechanisms
Solution Approach 2:
The patent creates a copy of the weight pattern data and stores it in an alternative arrangement within the memory array that avoids defective cells. This copied weight pattern is then used during neural network operation, allowing the system to function correctly despite the presence of defective cells in the original memory array, thereby avoiding the need for cell replacement while maintaining accuracy
3Reliability
If weight patterns are rearranged to avoid defects, then defect tolerance improves, but computational complexity increases
Solution Approach 1:
The patent segments the weight pattern data into smaller units and rearranges them in a systematic manner that avoids defective cells. By dividing the weight pattern into manageable segments and placing them in alternative locations within the memory array, the system achieves defect tolerance through a modular approach that simplifies the rearrangement process and reduces computational complexity
Data Source
AI summary
Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.