Semiconductor Memory Device Integrating Neural Network Operations

Solution Overview

Problem

The challenge is to provide a semiconductor memory device that supports machine learning operations while minimizing data communication traffic with external devices, as existing solutions require significant resources and are inefficient in real-world applications.

Innovation Solution

The semiconductor memory device includes a memory cell array with first and second memory cells, a row decoder block, a write and sense block, and an operation block, which performs operations such as multiplication, accumulation, and non-linear function applications within the device, reducing the need for external resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If machine learning operations are performed using external computing devices, then operation capability is achieved, but data communication traffic and resource usage increase

Engineering Contradiction:

Improvemachine learning operation capabilityVSAvoiddata communication traffic

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The patent combines memory storage functions with neural network operation functions into a single integrated device. The memory device includes both memory cells for data storage and an operation block for performing neural network operations (multiplication, accumulation, activation functions), eliminating the need for separate external computing devices and reducing data communication traffic.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The memory device is designed to perform multiple functions: it can store data in memory cells and simultaneously perform neural network operations using the stored data. The operation block can execute various operations including multiplication, accumulation, and activation functions, making the device versatile for different machine learning tasks.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If machine learning operations are performed using external computing devices, then operation capability is achieved, but resource consumption increases

Engineering Contradiction:

Improvemachine learning operation capabilityVSAvoidresource consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent combines memory storage functions with neural network operation functions into a single integrated device. The memory device includes both memory cells for data storage and an operation block for performing neural network operations (multiplication, accumulation, activation functions), eliminating the need for separate external computing devices and reducing data communication traffic.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If data is frequently communicated with external devices for neural network operations, then operation flexibility is maintained, but operation speed decreases

Engineering Contradiction:

Improveoperation flexibilityVSAvoidoperation speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent combines memory storage functions with neural network operation functions into a single integrated device. The memory device includes both memory cells for data storage and an operation block for performing neural network operations (multiplication, accumulation, activation functions), eliminating the need for separate external computing devices and reducing data communication traffic.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10818347B2Semiconductor memory device for supporting operation of neural network and operating method of semiconductor memory device

Publication Date: 2020.10.27 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.