3D Memory Nitride Layer Stack for Hydrogen Diffusion Control
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Solution Overview
Problem
In semiconductor memory devices, the diffusion of hydrogen ions through nitride layers can lead to fluctuations in the threshold voltage of transistors, affecting the device's performance, particularly when using nitride layers formed by different deposition techniques like PVD and CVD, which introduce varying hydrogen content and etching rates.
Innovation Solution
The implementation of a semiconductor memory device structure where a first nitride layer with lower hydrogen content is placed between the control circuit and the memory cell array, and a second nitride layer with higher hydrogen content is positioned between the control circuit and the first nitride layer, preventing hydrogen ion diffusion and maintaining stable transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nitride layer is formed by CVD deposition, then the nitride layer has higher hydrogen content which can be used to passivate interface states, but the hydrogen ions diffuse through the layer causing fluctuations in transistor threshold voltage
Solution Approach 1:
The patent divides the nitride layer into two separate layers: a first nitride layer (lower hydrogen content) positioned closer to the transistor to minimize threshold voltage fluctuations, and a second nitride layer (higher hydrogen content) positioned farther away to provide interface state passivation. This segmentation allows each layer to optimize its function independently.
Solution Approach 2:
The patent applies different quality characteristics to different regions by using nitride layers with distinct hydrogen content levels at different positions. The lower hydrogen content near the transistor reduces harmful diffusion, while the higher hydrogen content farther away provides passivation, creating a spatial gradient of material properties.
2Device complexity
If a single nitride layer is used between control circuit and memory cell array, then the structure is simple, but it cannot simultaneously minimize hydrogen ion diffusion and provide effective interface passivation
Solution Approach 1:
The single nitride layer is segmented into two distinct layers with different hydrogen content characteristics. This segmentation enables the structure to simultaneously achieve threshold voltage stability (through the lower hydrogen content layer) and interface passivation (through the higher hydrogen content layer), resolving the contradiction between simplicity and reliability.
3Adaptability or versatility
If nitride layers with different deposition techniques are used, then varying hydrogen content and etching rates can be achieved, but controlling the precise hydrogen ion diffusion becomes more difficult
Solution Approach 1:
The patent utilizes local quality by positioning nitride layers with specifically controlled hydrogen content at different locations. The lower hydrogen content layer is placed where precise diffusion control is critical (near the transistor), while the higher hydrogen content layer is placed where versatility in passivation is beneficial (farther away), optimizing both adaptability and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes the impact of hydrogen ions on the transistor threshold voltage, ensuring consistent performance and reliability in the semiconductor memory device.
Implementation Method 1
a first nitride layer arranged between the control circuit and the memory cell array, and a second nitride layer arranged between the control circuit and the first nitride layer
Data Source
AI summary
According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer.