Memory Device Noise Coupling via Segmented Connection Patterns
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Solution Overview
Problem
Existing memory devices face challenges in reducing noise coupling between bit lines and word lines during read and write operations, which affects efficiency and yield.
Innovation Solution
The memory device employs specific connection patterns for memory cells to bit lines and word lines, allowing for self-cancelation of noise between bit lines and word lines, thereby improving efficiency and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are connected to bit lines and word lines during read/write operations, then data access functionality is achieved, but noise coupling between bit lines and word lines occurs
Solution Approach 1:
The patent applies the 'Blessing in disguise' principle by utilizing the inherent coupling effect between bit lines and word lines to cancel noise. Specifically, during read operations, the coupling noise induced on bit lines by word line switching is counterbalanced by simultaneously switching complementary word lines, converting the harmful coupling effect into a beneficial noise cancellation mechanism. This allows data access functionality to be maintained while reducing noise coupling interference.
2Reliability
If conventional connection patterns are used for memory cells, then device simplicity is maintained, but noise interference affects operation yield
Solution Approach 1:
The patent applies the 'Segmentation' principle by dividing the memory array into multiple sub-arrays with different connection patterns. Each sub-array uses a specific connection pattern (e.g., even-row sub-arrays connected to even word lines, odd-row sub-arrays connected to odd word lines), allowing noise cancellation to be achieved through coordinated switching of segmented sub-arrays while maintaining overall device functionality and manageable complexity.
3Productivity
If memory operations are performed with high speed, then productivity is improved, but noise coupling between lines increases
Solution Approach 1:
The patent applies the 'Periodic action' principle by implementing alternating switching patterns of complementary word lines during memory operations. Instead of continuous switching, the system periodically alternates between switching even-word lines and odd-word lines in a coordinated manner, which maintains high operation speed while allowing noise cancellation to occur during each switching cycle, thereby reducing cumulative noise coupling effects.
Data Source
AI summary
A memory device is provided. A first sub-block of the memory device includes first memory cells arranged in a first row and connected to a first bit line and second of memory cells arranged in a second row and connected to a first complementary bit line. The first memory cells and the second memory cells are connected to word lines in a first connection pattern. A second sub-block of the memory device includes third memory cells arranged in a third row and connected to a second bit line and fourth memory cells arranged in a fourth row and connected to a complementary second bit line. The third memory cells and the fourth memory cells are connected to the word lines in a second connection pattern that is different from the first connection pattern.